/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
+#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
/* MII Status Register */
#define MII_STATUS_REG 1
int phy_addr;
int slave_port;
int sgmii_link_type;
+ struct phy_device *phy_dev;
};
int keystone2_emac_initialize(struct eth_priv_t *eth_priv);