use -ffunction-sections / --gc-sections on IXP42x

[u-boot] / arch / arm / lib / cache-cp15.c

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index b2811f35a6c9caf94c841365b89077b42290b047..d9175f058327fabf4f91ee0d751a043e4b0c0133 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -44,24 +44,33 @@ static void cp_delay (void)
        asm volatile("" : : : "memory");
 }
 
-/* to activate the MMU we need to set up virtual memory: use 1M areas in bss */
-static inline void mmu_setup(void)
+static inline void dram_bank_mmu_setup(int bank)
 {
-       static u32 __attribute__((aligned(16384))) page_table[4096];
+       u32 *page_table = (u32 *)gd->tlb_addr;
        bd_t *bd = gd->bd;
-       int i, j;
+       int     i;
+
+       debug("%s: bank: %d\n", __func__, bank);
+       for (i = bd->bi_dram[bank].start >> 20;
+            i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
+            i++) {
+               page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
+       }
+}
+
+/* to activate the MMU we need to set up virtual memory: use 1M areas */
+static inline void mmu_setup(void)
+{
+       u32 *page_table = (u32 *)gd->tlb_addr;
+       int i;
        u32 reg;
 
        /* Set up an identity-mapping for all 4GB, rw for everyone */
        for (i = 0; i < 4096; i++)
                page_table[i] = i << 20 | (3 << 10) | 0x12;
-       /* Then, enable cacheable and bufferable for RAM only */
-       for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
-               for (i = bd->bi_dram[j].start >> 20;
-                       i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20;
-                       i++) {
-                       page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
-               }
+
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               dram_bank_mmu_setup(i);
        }
 
        /* Copy the page table address to cp15 */
@@ -74,7 +83,6 @@ static inline void mmu_setup(void)
        reg = get_cr(); /* get control reg. */
        cp_delay();
        set_cr(reg | CR_M);
-
 }
 
 /* cache_bit must be either CR_I or CR_C */
@@ -96,6 +104,10 @@ static void cache_disable(uint32_t cache_bit)
        uint32_t reg;
 
        if (cache_bit == CR_C) {
+               /* if cache isn;t enabled no need to disable */
+               reg = get_cr();
+               if ((reg & CR_C) != CR_C)
+                       return;
                /* if disabling data cache, disable mmu too */
                cache_bit |= CR_M;
                flush_cache(0, ~0);