Merge branch 'master' of git://git.denx.de/u-boot-usb

[u-boot] / arch / arm / lib / cache-cp15.c

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index ba73fb925cfc8372bdcf18fa04a78304b7255102..e6c3eae6f9d2dad1b0bfe2f73d58922439870afa 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -34,6 +34,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void __arm_init_before_mmu(void)
+{
+}
+void arm_init_before_mmu(void)
+       __attribute__((weak, alias("__arm_init_before_mmu")));
+
 static void cp_delay (void)
 {
        volatile int i;
@@ -65,6 +71,7 @@ static inline void mmu_setup(void)
        int i;
        u32 reg;
 
+       arm_init_before_mmu();
        /* Set up an identity-mapping for all 4GB, rw for everyone */
        for (i = 0; i < 4096; i++)
                page_table[i] = i << 20 | (3 << 10) | 0x12;
@@ -85,13 +92,18 @@ static inline void mmu_setup(void)
        set_cr(reg | CR_M);
 }
 
+static int mmu_enabled(void)
+{
+       return get_cr() & CR_M;
+}
+
 /* cache_bit must be either CR_I or CR_C */
 static void cache_enable(uint32_t cache_bit)
 {
        uint32_t reg;
 
        /* The data cache is not active unless the mmu is enabled too */
-       if (cache_bit == CR_C)
+       if ((cache_bit == CR_C) && !mmu_enabled())
                mmu_setup();
        reg = get_cr(); /* get control reg. */
        cp_delay();
@@ -110,7 +122,7 @@ static void cache_disable(uint32_t cache_bit)
                        return;
                /* if disabling data cache, disable mmu too */
                cache_bit |= CR_M;
-               flush_cache(0, ~0);
+               flush_dcache_all();
        }
        reg = get_cr();
        cp_delay();