Kconfig: Add CONFIG_SATA to enable SATA

[u-boot] / arch / arm / lib / cache-cp15.c

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e9f9fc98f736d0e2f07cd3f9eb7b90279658fbce..f0c1b03728be3bca6ff16e0ded0abb4eeb19abae 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -22,16 +22,6 @@ __weak void arm_init_domains(void)
 {
 }
 
-static void cp_delay (void)
-{
-       volatile int i;
-
-       /* copro seems to need some delay between reading and writing */
-       for (i = 0; i < 100; i++)
-               nop();
-       asm volatile("" : : : "memory");
-}
-
 void set_section_dcache(int section, enum dcache_option option)
 {
 #ifdef CONFIG_ARMV7_LPAE
@@ -71,8 +61,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 
        end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
        start = start >> MMU_SECTION_SHIFT;
+#ifdef CONFIG_ARMV7_LPAE
+       debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
+             option);
+#else
        debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
              option);
+#endif
        for (upto = start; upto < end; upto++)
                set_section_dcache(upto, option);
 
@@ -124,7 +119,7 @@ static inline void mmu_setup(void)
                dram_bank_mmu_setup(i);
        }
 
-#ifdef CONFIG_ARMV7_LPAE
+#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
        /* Set up 4 PTE entries pointing to our 4 1GB page tables */
        for (i = 0; i < 4; i++) {
                u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
@@ -142,7 +137,7 @@ static inline void mmu_setup(void)
 #endif
 
        if (is_hyp()) {
-               /* Set HCTR to enable LPAE */
+               /* Set HTCR to enable LPAE */
                asm volatile("mcr p15, 4, %0, c2, c0, 2"
                        : : "r" (reg) : "memory");
                /* Set HTTBR0 */
@@ -167,6 +162,15 @@ static inline void mmu_setup(void)
                        : : "r" (MEMORY_ATTRIBUTES) : "memory");
        }
 #elif defined(CONFIG_CPU_V7)
+       if (is_hyp()) {
+               /* Set HTCR to disable LPAE */
+               asm volatile("mcr p15, 4, %0, c2, c0, 2"
+                       : : "r" (0) : "memory");
+       } else {
+               /* Set TTBCR to disable LPAE */
+               asm volatile("mcr p15, 0, %0, c2, c0, 2"
+                       : : "r" (0) : "memory");
+       }
        /* Set TTBR0 */
        reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
@@ -191,7 +195,6 @@ static inline void mmu_setup(void)
 
        /* and enable the mmu */
        reg = get_cr(); /* get control reg. */
-       cp_delay();
        set_cr(reg | CR_M);
 }
 
@@ -209,7 +212,6 @@ static void cache_enable(uint32_t cache_bit)
        if ((cache_bit == CR_C) && !mmu_enabled())
                mmu_setup();
        reg = get_cr(); /* get control reg. */
-       cp_delay();
        set_cr(reg | cache_bit);
 }
 
@@ -219,7 +221,6 @@ static void cache_disable(uint32_t cache_bit)
        uint32_t reg;
 
        reg = get_cr();
-       cp_delay();
 
        if (cache_bit == CR_C) {
                /* if cache isn;t enabled no need to disable */
@@ -229,7 +230,7 @@ static void cache_disable(uint32_t cache_bit)
                cache_bit |= CR_M;
        }
        reg = get_cr();
-       cp_delay();
+
        if (cache_bit == (CR_C | CR_M))
                flush_dcache_all();
        set_cr(reg & ~cache_bit);