# error You need to define CONFIG_AT91FAMILY in your board config!
#endif
+#define EN_PLLB_TIMEOUT 500
+
DECLARE_GLOBAL_DATA_PTR;
static unsigned long at91_css_to_rate(unsigned long css)
gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = gd->arch.mck_rate_hz;
+#if defined(CONFIG_AT91SAM9X5)
+ /* different in prescale on at91sam9x5 */
+ freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4));
+#else
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
+#endif
+
#if defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
;
}
-void at91_periph_clk_enable(int id)
+int at91_pllb_clk_enable(u32 pllbr)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+ ulong start_time, tmp_time;
+
+ start_time = get_timer(0);
+ writel(pllbr, &pmc->pllbr);
+ while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
+ tmp_time = get_timer(0);
+ if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
+ printf("ERROR: failed to enable PLLB\n");
+ return -1;
+ }
+ }
- writel(1 << id, &pmc->pcer);
+ return 0;
+}
+
+int at91_pllb_clk_disable(void)
+{
+ struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+ ulong start_time, tmp_time;
+
+ start_time = get_timer(0);
+ writel(0, &pmc->pllbr);
+ while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
+ tmp_time = get_timer(0);
+ if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
+ printf("ERROR: failed to disable PLLB\n");
+ return -1;
+ }
+ }
+
+ return 0;
}