ARM: am33xx: Always inhibit init/refresh during DDR phy init

[u-boot] / arch / arm / mach-exynos / clock.c

diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 1c6baa14b213ef839d4864d6d16ff1e28a07672e..3d31f9d524909716ee3785139614d4d80366aefa 100644 (file)
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -159,8 +159,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
                        div = PLL_DIV_1024;
                else if (proid_is_exynos4412())
                        div = PLL_DIV_65535;
-               else if (proid_is_exynos5250() || proid_is_exynos5420()
-                        || proid_is_exynos5800())
+               else if (proid_is_exynos5250() || proid_is_exynos5420() ||
+                        proid_is_exynos5422())
                        div = PLL_DIV_65536;
                else
                        return 0;
@@ -346,7 +346,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
        int i;
        struct clk_bit_info *info;
 
-       if (proid_is_exynos5420() || proid_is_exynos5800())
+       if (proid_is_exynos5420() || proid_is_exynos5422())
                info = exynos542x_bit_info;
        else
                info = exynos5_bit_info;
@@ -558,7 +558,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral)
 unsigned long clock_get_periph_rate(int peripheral)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420() || proid_is_exynos5800())
+               if (proid_is_exynos5420() || proid_is_exynos5422())
                        return exynos542x_get_periph_rate(peripheral);
                return exynos5_get_periph_rate(peripheral);
        } else {
@@ -1576,7 +1576,7 @@ static unsigned long exynos4_get_i2c_clk(void)
 unsigned long get_pll_clk(int pllreg)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420() || proid_is_exynos5800())
+               if (proid_is_exynos5420() || proid_is_exynos5422())
                        return exynos542x_get_pll_clk(pllreg);
                return exynos5_get_pll_clk(pllreg);
        } else if (cpu_is_exynos4()) {
@@ -1661,6 +1661,9 @@ unsigned long get_mmc_clk(int dev_index)
 {
        enum periph_id id;
 
+       if (cpu_is_exynos4())
+               return exynos4_get_mmc_clk(dev_index);
+
        switch (dev_index) {
        case 0:
                id = PERIPH_ID_SDMMC0;
@@ -1679,12 +1682,7 @@ unsigned long get_mmc_clk(int dev_index)
                return -1;
        }
 
-       if (cpu_is_exynos5())
-               return clock_get_periph_rate(id);
-       else if (cpu_is_exynos4())
-               return exynos4_get_mmc_clk(dev_index);
-
-       return 0;
+       return clock_get_periph_rate(id);
 }
 
 void set_mmc_clk(int dev_index, unsigned int div)
@@ -1694,7 +1692,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
                div -= 1;
 
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420() || proid_is_exynos5800())
+               if (proid_is_exynos5420() || proid_is_exynos5422())
                        exynos5420_set_mmc_clk(dev_index, div);
                else
                        exynos5_set_mmc_clk(dev_index, div);
@@ -1710,7 +1708,7 @@ unsigned long get_lcd_clk(void)
        } else if (cpu_is_exynos5()) {
                if (proid_is_exynos5420())
                        return exynos5420_get_lcd_clk();
-               else if (proid_is_exynos5800())
+               else if (proid_is_exynos5422())
                        return exynos5800_get_lcd_clk();
                else
                        return exynos5_get_lcd_clk();
@@ -1742,7 +1740,7 @@ void set_mipi_clk(void)
 int set_spi_clk(int periph_id, unsigned int rate)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420() || proid_is_exynos5800())
+               if (proid_is_exynos5420() || proid_is_exynos5422())
                        return exynos5420_set_spi_clk(periph_id, rate);
                return exynos5_set_spi_clk(periph_id, rate);
        }