Merge branch 'master' of http://git.denx.de/u-boot-sunxi

[u-boot] / arch / arm / mach-exynos / dmc_init_ddr3.c

diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index 7c0b12ae51addbffee5af54128ddd2f57a539adf..25a9df936479c8ce18a01e5b676e81ea096294e2 100644 (file)
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c
@@ -20,8 +20,8 @@
 #define TIMEOUT_US             10000
 #define NUM_BYTE_LANES         4
 #define DEFAULT_DQS            8
-#define DEFAULT_DQS_X4         (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
-                               || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
+#define DEFAULT_DQS_X4         ((DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+                               || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0))
 
 #ifdef CONFIG_EXYNOS5250
 static void reset_phy_ctrl(void)
@@ -856,10 +856,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
         */
        val = readl(&drex0->concontrol);
        val |= CONCONTROL_UPDATE_MODE;
-       writel(val , &drex0->concontrol);
+       writel(val, &drex0->concontrol);
        val = readl(&drex1->concontrol);
        val |= CONCONTROL_UPDATE_MODE;
-       writel(val , &drex1->concontrol);
+       writel(val, &drex1->concontrol);
 
        return 0;
 }