enable_pll3();
}
+#ifdef CONFIG_MTD_NOR_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
return 0;
}
+#ifndef CONFIG_SPL_BUILD
/*
* Dump some core clockes.
*/
}
#endif
-#ifdef CONFIG_MTD_NOR_FLASH
-void enable_eim_clk(unsigned char enable)
-{
- u32 reg;
-
- reg = __raw_readl(&imx_ccm->CCGR6);
- if (enable)
- reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
- else
- reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
- __raw_writel(reg, &imx_ccm->CCGR6);
-}
-#endif
-
/***************************************************/
U_BOOT_CMD(
"display clocks",
""
);
+#endif