]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/mach-imx/mx6/clock.c
imx6: disable clock command and print_cpuinfo code in SPL
[u-boot] / arch / arm / mach-imx / mx6 / clock.c
index 0e019c42622f8a4c2b7c0094cf0161646ab83c2b..71a9e6bca0fee4ca8af82e79d912ff02da6bd203 100644 (file)
@@ -1220,6 +1220,20 @@ void enable_thermal_clk(void)
        enable_pll3();
 }
 
+#ifdef CONFIG_MTD_NOR_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+       u32 reg;
+
+       reg = __raw_readl(&imx_ccm->CCGR6);
+       if (enable)
+               reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+       else
+               reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+       __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
        switch (clk) {
@@ -1262,6 +1276,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
        return 0;
 }
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
@@ -1463,20 +1478,6 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
 }
 #endif
 
-#ifdef CONFIG_MTD_NOR_FLASH
-void enable_eim_clk(unsigned char enable)
-{
-       u32 reg;
-
-       reg = __raw_readl(&imx_ccm->CCGR6);
-       if (enable)
-               reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
-       else
-               reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
-       __raw_writel(reg, &imx_ccm->CCGR6);
-}
-#endif
-
 /***************************************************/
 
 U_BOOT_CMD(
@@ -1484,3 +1485,4 @@ U_BOOT_CMD(
        "display clocks",
        ""
 );
+#endif