Merge git://git.denx.de/u-boot-spi

[u-boot] / arch / arm / mach-imx / mx6 / ddr.c

diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 39dbd2f60728a98787ca108c03d4afb56270c47e..43b77cfa4166609cf3ce6d71e74d12b612f6c224 100644 (file)
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -21,10 +21,10 @@ static void reset_read_data_fifos(void)
 
        /* Reset data FIFOs twice. */
        setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
-       wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
 
        setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
-       wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
 }
 
 static void precharge_all(const bool cs0_enable, const bool cs1_enable)
@@ -39,12 +39,12 @@ static void precharge_all(const bool cs0_enable, const bool cs1_enable)
         */
        if (cs0_enable) { /* CS0 */
                writel(0x04008050, &mmdc0->mdscr);
-               wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+               wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
        }
 
        if (cs1_enable) { /* CS1 */
                writel(0x04008058, &mmdc0->mdscr);
-               wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+               wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
        }
 }
 
@@ -146,7 +146,7 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
         * 7. Upon completion of this process the MMDC de-asserts
         * the MPWLGCR[HW_WL_EN]
         */
-       wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
 
        /*
         * 8. check for any errors: check both PHYs for x64 configuration,
@@ -278,7 +278,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
                writel(0x00008028, &mmdc0->mdscr);
 
        /* poll to make sure the con_ack bit was asserted */
-       wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+       wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
 
        /*
         * Check MDMISC register CALIB_PER_CS to see which CS calibration
@@ -312,7 +312,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
         * this bit until it clears to indicate completion of the write access.
         */
        setbits_le32(&mmdc0->mpswdar0, 1);
-       wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
 
        /* Set the RD_DL_ABS# bits to their default values
         * (will be calibrated later in the read delay-line calibration).
@@ -359,7 +359,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
        setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
 
        /* Poll for completion.  MPDGCTRL0[HW_DG_EN] should be 0 */
-       wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
 
        /*
         * Check to see if any errors were encountered during calibration
@@ -423,7 +423,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
         * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0.   Also, ensure that
         * no error bits were set.
         */
-       wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
 
        /* check both PHYs for x64 configuration, if x32, check only PHY0 */
        if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
@@ -477,7 +477,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
         * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
         * Also, ensure that no error bits were set.
         */
-       wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
 
        /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
        if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
@@ -526,7 +526,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
        writel(0x0, &mmdc0->mdscr);     /* CS0 */
 
        /* Poll to make sure the con_ack bit is clear */
-       wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
 
        /*
         * Print out the registers that were updated as a result