ARM: mx6: ddr: Add write leveling correction code

[u-boot] / arch / arm / mach-imx / mx6 / ddr.c

diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 43b77cfa4166609cf3ce6d71e74d12b612f6c224..6e5e40dd1ae8e2d64bc640a15df6edac5741ee57 100644 (file)
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -85,6 +85,23 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
        writel(val_ctrl, reg_ctrl);
 }
 
+static void correct_mpwldectr_result(void *reg)
+{
+       /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
+       const unsigned int limit = 0x148;
+       u32 val = readl(reg);
+       u32 old = val;
+
+       if ((val & 0x17f) > limit)
+               val &= 0xffff << 16;
+
+       if (((val >> 16) & 0x17f) > limit)
+               val &= 0xffff;
+
+       if (old != val)
+               writel(val, reg);
+}
+
 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 {
        struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
@@ -176,6 +193,13 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
                errors |= 4;
        }
 
+       correct_mpwldectr_result(&mmdc0->mpwldectrl0);
+       correct_mpwldectr_result(&mmdc0->mpwldectrl1);
+       if (sysinfo->dsize == 2) {
+               correct_mpwldectr_result(&mmdc1->mpwldectrl0);
+               correct_mpwldectr_result(&mmdc1->mpwldectrl1);
+       }
+
        /*
         * User should issue MRS command to exit write leveling mode
         * through Load Mode Register command