#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
reg = KS2_PASSPLLCTL0;
break;
case DDR3_PLL:
- ret = external_clk[ddr3_clk];
+ ret = external_clk[ddr3a_clk];
reg = KS2_DDR3APLLCTL0;
break;
default: