ARM: allocate extra space for PSCI stack in secure section during link phase

[u-boot] / arch / arm / mach-keystone / clock.c

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index fc3eadb3f27937a92b9e59d54bf0383227fc958e..b25db1e3fedefc1cce20fec1aa9eec75435bbdc1 100644 (file)
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -31,8 +31,14 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
        [TETRIS_PLL]    = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
        [DDR3A_PLL]     = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
        [DDR3B_PLL]     = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+       [UART_PLL]      = {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
 };
 
+inline void pll_pa_clk_sel(void)
+{
+       setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK);
+}
+
 static void wait_for_completion(const struct pll_init_data *data)
 {
        int i;
@@ -180,9 +186,8 @@ void configure_secondary_pll(const struct pll_init_data *data)
        sdelay(21000);
 
        /* Select the Output of PASS PLL as input to PASS */
-       if (data->pll == PASS_PLL)
-               setbits_le32(keystone_pll_regs[data->pll].reg1,
-                            CFG_PLLCTL1_PAPLL_MASK);
+       if (data->pll == PASS_PLL && cpu_is_k2hk())
+               pll_pa_clk_sel();
 
        /* Select the Output of ARM PLL as input to ARM */
        if (data->pll == TETRIS_PLL)
@@ -223,18 +228,21 @@ void init_plls(void)
        }
 }
 
-static int get_max_speed(u32 val, u32 speed_supported)
+static int get_max_speed(u32 val, u32 speed_supported, int *spds)
 {
        int speed;
 
        /* Left most setbit gives the speed */
        for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
                if ((val & BIT(speed)) & speed_supported)
-                       return speeds[speed];
+                       return spds[speed];
        }
 
-       /* If no bit is set, use SPD800 */
-       return SPD800;
+       /* If no bit is set, return minimum speed */
+       if (cpu_is_k2g())
+               return SPD200;
+       else
+               return SPD800;
 }
 
 static inline u32 read_efuse_bootrom(void)
@@ -245,24 +253,24 @@ static inline u32 read_efuse_bootrom(void)
                return __raw_readl(KS2_EFUSE_BOOTROM);
 }
 
-int get_max_arm_speed(void)
+int get_max_arm_speed(int *spds)
 {
        u32 armspeed = read_efuse_bootrom();
 
        armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
                    DEVSPEED_ARMSPEED_SHIFT;
 
-       return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS);
+       return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS, spds);
 }
 
-int get_max_dev_speed(void)
+int get_max_dev_speed(int *spds)
 {
        u32 devspeed = read_efuse_bootrom();
 
        devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
                    DEVSPEED_DEVSPEED_SHIFT;
 
-       return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
+       return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS, spds);
 }
 
 /**
@@ -309,6 +317,10 @@ static unsigned long pll_freq_get(int pll)
                        ret = external_clk[ddr3b_clk];
                        reg = KS2_DDR3BPLLCTL0;
                        break;
+               case UART_PLL:
+                       ret = external_clk[uart_clk];
+                       reg = KS2_UARTPLLCTL0;
+                       break;
                default:
                        return 0;
                }
@@ -351,6 +363,10 @@ unsigned long clk_get_rate(unsigned int clk)
                if (cpu_is_k2hk())
                        freq = pll_freq_get(DDR3B_PLL);
                break;
+       case uart_pll_clk:
+               if (cpu_is_k2g())
+                       freq = pll_freq_get(UART_PLL);
+               break;
        case sys_clk0_1_clk:
        case sys_clk0_clk:
                freq = pll_freq_get(CORE_PLL) / pll0div_read(1);