sunxi: Add base address for GIC

[u-boot] / arch / arm / mach-keystone / init.c

diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index aadd10bff2705c1b9f17d7f5aa9390dd602aad56..3b6d5efce1a1386f2203d5e75b0e46892612e47f 100644 (file)
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -96,22 +96,81 @@ static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
        __raw_writel(val, KS2_DEVCFG);
 }
 
+static void msmc_k2hkle_common_setup(void)
+{
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
+       msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
+       msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
+#ifdef KS2_MSMC_SEGMENT_QM_PDSP
+       msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
+#endif
+       msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
+}
+
+static void msmc_k2hk_setup(void)
+{
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
+       msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
+}
+
+static inline void msmc_k2l_setup(void)
+{
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
+       msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
+}
+
+static inline void msmc_k2e_setup(void)
+{
+       msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
+       msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
+       msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
+}
+
+static void msmc_k2g_setup(void)
+{
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
+       msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
+}
+
 int arch_cpu_init(void)
 {
        chip_configuration_unlock();
        icache_enable();
 
-       msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
-       msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
-#ifdef KS2_MSMC_SEGMENT_QM_PDSP
-       msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
-#endif
-       msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+       if (cpu_is_k2g()) {
+               msmc_k2g_setup();
+       } else {
+               msmc_k2hkle_common_setup();
+               if (cpu_is_k2e())
+                       msmc_k2e_setup();
+               else if (cpu_is_k2l())
+                       msmc_k2l_setup();
+               else
+                       msmc_k2hk_setup();
+       }
 
        /* Initialize the PCIe-0 to work as Root Complex */
        config_pcie_mode(0, ROOTCOMPLEX);
 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
-       msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
        /* Initialize the PCIe-1 to work as Root Complex */
        config_pcie_mode(1, ROOTCOMPLEX);
 #endif