return 0;
}
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
/* Reserve first 16 MiB of RAM for firmware */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
- gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
+ gd->bd->bi_dram[0].start = 0x1000000;
+ gd->bd->bi_dram[0].size = 0xf000000;
+ /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
+ gd->bd->bi_dram[1].start = 0x10000000;
+ gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000;
+ return 0;
}
void reset_cpu(ulong addr)
{
- psci_system_reset(true);
+ psci_system_reset();
}
static struct mm_region gxbb_mem_map[] = {
{
- .base = 0x0UL,
+ .virt = 0x0UL,
+ .phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
- .base = 0x80000000UL,
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |