Merge branch 'master' of git://git.denx.de/u-boot-i2c; branch 'master' of git://git...

[u-boot] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 6ea558c69fd3a31a9c0ad78847f5a2a455a91fb0..30b175c64657111fcd536bb6a7bf80f0c7553490 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -49,25 +49,24 @@ int mvebu_soc_family(void)
 {
        u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
 
-       if ((devid == SOC_MV78260_ID) || (devid == SOC_MV78460_ID))
+       switch (devid) {
+       case SOC_MV78230_ID:
+       case SOC_MV78260_ID:
+       case SOC_MV78460_ID:
                return MVEBU_SOC_AXP;
-
-       if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
-           devid == SOC_88F6828_ID)
+       case SOC_88F6810_ID:
+       case SOC_88F6820_ID:
+       case SOC_88F6828_ID:
                return MVEBU_SOC_A38X;
-
+       }
        return MVEBU_SOC_UNKNOWN;
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 
 #if defined(CONFIG_ARMADA_38X)
-/* SAR values for Armada 38x */
-#define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18600))
-#define SAR_CPU_FREQ_OFFS      10
-#define SAR_CPU_FREQ_MASK      (0x1f << SAR_CPU_FREQ_OFFS)
-
-struct sar_freq_modes sar_freq_tab[] = {
+/* SAR frequency values for Armada 38x */
+static const struct sar_freq_modes sar_freq_tab[] = {
        {  0x0,  0x0,  666, 333, 333 },
        {  0x2,  0x0,  800, 400, 400 },
        {  0x4,  0x0, 1066, 533, 533 },
@@ -77,17 +76,8 @@ struct sar_freq_modes sar_freq_tab[] = {
        { 0xff, 0xff,    0,   0,   0 }  /* 0xff marks end of array */
 };
 #else
-/* SAR values for Armada XP */
-#define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18230))
-#define CONFIG_SAR2_REG                (MVEBU_REGISTER(0x18234))
-#define SAR_CPU_FREQ_OFFS      21
-#define SAR_CPU_FREQ_MASK      (0x7 << SAR_CPU_FREQ_OFFS)
-#define SAR_FFC_FREQ_OFFS      24
-#define SAR_FFC_FREQ_MASK      (0xf << SAR_FFC_FREQ_OFFS)
-#define SAR2_CPU_FREQ_OFFS     20
-#define SAR2_CPU_FREQ_MASK     (0x1 << SAR2_CPU_FREQ_OFFS)
-
-struct sar_freq_modes sar_freq_tab[] = {
+/* SAR frequency values for Armada XP */
+static const struct sar_freq_modes sar_freq_tab[] = {
        {  0xa,  0x5,  800, 400, 400 },
        {  0x1,  0x5, 1066, 533, 533 },
        {  0x2,  0x5, 1200, 600, 600 },
@@ -153,6 +143,9 @@ int print_cpuinfo(void)
        puts("SoC:   ");
 
        switch (devid) {
+       case SOC_MV78230_ID:
+               puts("MV78230-");
+               break;
        case SOC_MV78260_ID:
                puts("MV78260-");
                break;