ARM: keystone2: Cleanup SoC detection

[u-boot] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 8058fadb22baa1cb52f2744ba63b4d91615078df..9496d5fc5b9b153257e54d0ef0bb56b47f74b787 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -6,9 +6,13 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <ahci.h>
+#include <linux/mbus.h>
 #include <asm/io.h>
+#include <asm/pl310.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <sdhci.h>
 
 #define DDR_BASE_CS_OFF(n)     (0x0000 + ((n) << 3))
 #define DDR_SIZE_CS_OFF(n)     (0x0004 + ((n) << 3))
@@ -159,11 +163,36 @@ static void update_sdram_window_sizes(void)
        }
 }
 
+void mmu_disable(void)
+{
+       asm volatile(
+               "mrc p15, 0, r0, c1, c0, 0\n"
+               "bic r0, #1\n"
+               "mcr p15, 0, r0, c1, c0, 0\n");
+}
+
 #ifdef CONFIG_ARCH_CPU_INIT
+static void set_cbar(u32 addr)
+{
+       asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
+}
+
+
 int arch_cpu_init(void)
 {
+#ifndef CONFIG_SPL_BUILD
+       /*
+        * Only with disabled MMU its possible to switch the base
+        * register address on Armada 38x. Without this the SDRAM
+        * located at >= 0x4000.0000 is also not accessible, as its
+        * still locked to cache.
+        */
+       mmu_disable();
+#endif
+
        /* Linux expects the internal registers to be at 0xf1000000 */
        writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+       set_cbar(SOC_REGS_PHY_BASE + 0xC000);
 
        /*
         * We need to call mvebu_mbus_probe() before calling
@@ -237,9 +266,82 @@ int cpu_eth_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MV_SDHCI
+int board_mmc_init(bd_t *bis)
+{
+       mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
+                   SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
+
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+#define AHCI_VENDOR_SPECIFIC_0_ADDR    0xa0
+#define AHCI_VENDOR_SPECIFIC_0_DATA    0xa4
+
+#define AHCI_WINDOW_CTRL(win)          (0x60 + ((win) << 4))
+#define AHCI_WINDOW_BASE(win)          (0x64 + ((win) << 4))
+#define AHCI_WINDOW_SIZE(win)          (0x68 + ((win) << 4))
+
+static void ahci_mvebu_mbus_config(void __iomem *base)
+{
+       const struct mbus_dram_target_info *dram;
+       int i;
+
+       dram = mvebu_mbus_dram_info();
+
+       for (i = 0; i < 4; i++) {
+               writel(0, base + AHCI_WINDOW_CTRL(i));
+               writel(0, base + AHCI_WINDOW_BASE(i));
+               writel(0, base + AHCI_WINDOW_SIZE(i));
+       }
+
+       for (i = 0; i < dram->num_cs; i++) {
+               const struct mbus_dram_window *cs = dram->cs + i;
+
+               writel((cs->mbus_attr << 8) |
+                      (dram->mbus_dram_target_id << 4) | 1,
+                      base + AHCI_WINDOW_CTRL(i));
+               writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
+               writel(((cs->size - 1) & 0xffff0000),
+                      base + AHCI_WINDOW_SIZE(i));
+       }
+}
+
+static void ahci_mvebu_regret_option(void __iomem *base)
+{
+       /*
+        * Enable the regret bit to allow the SATA unit to regret a
+        * request that didn't receive an acknowlegde and avoid a
+        * deadlock
+        */
+       writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
+       writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
+}
+
+void scsi_init(void)
+{
+       printf("MVEBU SATA INIT\n");
+       ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
+       ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
+       ahci_init((void __iomem *)MVEBU_SATA0_BASE);
+}
+#endif
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
+       struct pl310_regs *const pl310 =
+               (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+       /* First disable L2 cache - may still be enable from BootROM */
+       if (mvebu_soc_family() == MVEBU_SOC_A38X)
+               clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+       /* Avoid problem with e.g. neta ethernet driver */
+       invalidate_dcache_all();
+
        /* Enable D-cache. I-cache is already enabled in start.S */
        dcache_enable();
 }