#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
static struct mbus_win windows[] = {
- /* PCIE MEM address space */
- { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
-
- /* PCIE IO address space */
- { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
-
/* SPI */
- { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
- CPU_ATTR_SPIFLASH },
+ { MBUS_SPI_BASE, MBUS_SPI_SIZE,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
/* NOR */
- { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
- CPU_ATTR_BOOTROM },
+ { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
};
+void lowlevel_init(void)
+{
+ /*
+ * Dummy implementation, we only need LOWLEVEL_INIT
+ * on Armada to configure CP15 in start.S / cpu_init_cp15()
+ */
+}
+
void reset_cpu(unsigned long ignored)
{
struct mvebu_system_registers *reg =
asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
}
+#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
+#define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
+#define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
+ (((addr) & 0xF) << 6))
+#define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
+ (((reg) & 0xF) << 2))
+
+static void setup_usb_phys(void)
+{
+ int dev;
+
+ /*
+ * USB PLL init
+ */
+
+ /* Setup PLL frequency */
+ /* USB REF frequency = 25 MHz */
+ clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
+
+ /* Power up PLL and PHY channel */
+ clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9));
+
+ /* Assert VCOCAL_START */
+ clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21));
+
+ mdelay(1);
+
+ /*
+ * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
+ */
+
+ for (dev = 0; dev < 3; dev++) {
+ clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15));
+
+ /* Assert REG_RCAL_START in channel REG 1 */
+ clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12));
+ udelay(40);
+ clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0);
+ }
+}
int arch_cpu_init(void)
{
-#ifndef CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_BUILD)
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
/*
* Only with disabled MMU its possible to switch the base
* register address on Armada 38x. Without this the SDRAM
writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
set_cbar(SOC_REGS_PHY_BASE + 0xC000);
+#if !defined(CONFIG_SPL_BUILD)
+ /*
+ * From this stage on, the SoC detection is working. As we have
+ * configured the internal register base to the value used
+ * in the macros / defines in the U-Boot header (soc.h).
+ */
+
+ /*
+ * To fully release / unlock this area from cache, we need
+ * to flush all caches and disable the L2 cache.
+ */
+ icache_disable();
+ dcache_disable();
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+#endif
+
/*
* We need to call mvebu_mbus_probe() before calling
* update_sdram_window_sizes() as it disables all previously
*/
mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ /* Enable GBE0, GBE1, LCD and NFC PUP */
+ clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
+ GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
+ NAND_PUP_EN | SPI_PUP_EN);
+
+ /* Configure USB PLL and PHYs on AXP */
+ setup_usb_phys();
+ }
+
+ /* Enable NAND and NAND arbiter */
+ clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
+
+ /* Disable MBUS error propagation */
+ clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
+
return 0;
}
#endif /* CONFIG_ARCH_CPU_INIT */
+u32 mvebu_get_nand_clock(void)
+{
+ return CONFIG_SYS_MVEBU_PLL_CLOCK /
+ ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
+ NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
+}
+
/*
* SOC specific misc init
*/
}
#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_MVNETA
-int cpu_eth_init(bd_t *bis)
-{
- u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
- MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
- u8 phy_addr[] = CONFIG_PHY_ADDR;
- int i;
-
- /*
- * Only Armada XP supports all 4 ethernet interfaces. A38x has
- * slightly different base addresses for its 2-3 interfaces.
- */
- if (mvebu_soc_family() != MVEBU_SOC_AXP) {
- enet_base[1] = MVEBU_EGIGA2_BASE;
- enet_base[2] = MVEBU_EGIGA3_BASE;
- }
-
- for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
- mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_MV_SDHCI
int board_mmc_init(bd_t *bis)
{
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
- struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-
- /* First disable L2 cache - may still be enable from BootROM */
- if (mvebu_soc_family() == MVEBU_SOC_A38X)
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
-#endif
+
+void v7_outer_cache_enable(void)
+{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ /* The L2 cache is already disabled at this point */
+
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ u32 u;
+
+ /*
+ * For Aurora cache in no outer mode, enable via the CP15
+ * coprocessor broadcasting of cache commands to L2.
+ */
+ asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
+ u |= BIT(8); /* Set the FW bit */
+ asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
+
+ isb();
+
+ /* Enable the L2 cache */
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ }
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
projects / u-boot / blobdiff