arm: mvebu: Add v7_outer_cache_disable function for AXP & A38x

[u-boot] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index ea83e21d433cd6d639ce1bf0e54087f6720f2575..fd56c99c925501113e896a7f46005ced3d642449 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -27,6 +27,14 @@ static struct mbus_win windows[] = {
          CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
 };
 
+void lowlevel_init(void)
+{
+       /*
+        * Dummy implementation, we only need LOWLEVEL_INIT
+        * on Armada to configure CP15 in start.S / cpu_init_cp15()
+        */
+}
+
 void reset_cpu(unsigned long ignored)
 {
        struct mvebu_system_registers *reg =
@@ -214,32 +222,39 @@ static void setup_usb_phys(void)
 
 int arch_cpu_init(void)
 {
-#ifndef CONFIG_SPL_BUILD
-       if (mvebu_soc_family() == MVEBU_SOC_A38X) {
-               struct pl310_regs *const pl310 =
-                       (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#if !defined(CONFIG_SPL_BUILD)
+       struct pl310_regs *const pl310 =
+               (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
-               /*
-                * Only with disabled MMU its possible to switch the base
-                * register address on Armada 38x. Without this the SDRAM
-                * located at >= 0x4000.0000 is also not accessible, as its
-                * still locked to cache.
-                *
-                * So to fully release / unlock this area from cache, we need
-                * to first flush all caches, then disable the MMU and
-                * disable the L2 cache.
-                */
-               icache_disable();
-               dcache_disable();
-               mmu_disable();
-               clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-       }
+       /*
+        * Only with disabled MMU its possible to switch the base
+        * register address on Armada 38x. Without this the SDRAM
+        * located at >= 0x4000.0000 is also not accessible, as its
+        * still locked to cache.
+        */
+       mmu_disable();
 #endif
 
        /* Linux expects the internal registers to be at 0xf1000000 */
        writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
        set_cbar(SOC_REGS_PHY_BASE + 0xC000);
 
+#if !defined(CONFIG_SPL_BUILD)
+       /*
+        * From this stage on, the SoC detection is working. As we have
+        * configured the internal register base to the value used
+        * in the macros / defines in the U-Boot header (soc.h).
+        */
+
+       /*
+        * To fully release / unlock this area from cache, we need
+        * to flush all caches and disable the L2 cache.
+        */
+       icache_disable();
+       dcache_disable();
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+#endif
+
        /*
         * We need to call mvebu_mbus_probe() before calling
         * update_sdram_window_sizes() as it disables all previously
@@ -311,30 +326,6 @@ int arch_misc_init(void)
 }
 #endif /* CONFIG_ARCH_MISC_INIT */
 
-#ifdef CONFIG_MVNETA
-int cpu_eth_init(bd_t *bis)
-{
-       u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
-                           MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
-       u8 phy_addr[] = CONFIG_PHY_ADDR;
-       int i;
-
-       /*
-        * Only Armada XP supports all 4 ethernet interfaces. A38x has
-        * slightly different base addresses for its 2-3 interfaces.
-        */
-       if (mvebu_soc_family() != MVEBU_SOC_AXP) {
-               enet_base[1] = MVEBU_EGIGA2_BASE;
-               enet_base[2] = MVEBU_EGIGA3_BASE;
-       }
-
-       for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
-               mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
-
-       return 0;
-}
-#endif
-
 #ifdef CONFIG_MV_SDHCI
 int board_mmc_init(bd_t *bis)
 {
@@ -398,20 +389,44 @@ void scsi_init(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
-       struct pl310_regs *const pl310 =
-               (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-
-       /* First disable L2 cache - may still be enable from BootROM */
-       if (mvebu_soc_family() == MVEBU_SOC_A38X)
-               clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
        /* Avoid problem with e.g. neta ethernet driver */
        invalidate_dcache_all();
 
        /* Enable D-cache. I-cache is already enabled in start.S */
        dcache_enable();
 }
-#endif
+
+void v7_outer_cache_enable(void)
+{
+       struct pl310_regs *const pl310 =
+               (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+       /* The L2 cache is already disabled at this point */
+
+       if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+               u32 u;
+
+               /*
+                * For Aurora cache in no outer mode, enable via the CP15
+                * coprocessor broadcasting of cache commands to L2.
+                */
+               asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
+               u |= BIT(8);            /* Set the FW bit */
+               asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
+
+               isb();
+
+               /* Enable the L2 cache */
+               setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+       }
+}
+
+void v7_outer_cache_disable(void)
+{
+       struct pl310_regs *const pl310 =
+               (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}