#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#ifdef CONFIG_SYS_MVEBU_DDR_A38X
-#include "../../../drivers/ddr/marvell/a38x/ddr3_init.h"
-#endif
-#ifdef CONFIG_SYS_MVEBU_DDR_AXP
-#include "../../../drivers/ddr/marvell/axp/ddr3_init.h"
+#if defined(CONFIG_ARCH_MVEBU)
+/* Use common XOR definitions for A3x and AXP */
+#include "../../../drivers/ddr/marvell/axp/xor.h"
+#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
+#define SDRAM_SIZE_MAX 0xc0000000
+
+#define SCRUB_MAGIC 0xbeefdead
+
+#define SCRB_XOR_UNIT 0
+#define SCRB_XOR_CHAN 1
+#define SCRB_XOR_WIN 0
+
+#define XEBARX_BASE_OFFS 16
+
/*
* mvebu_sdram_bar - reads SDRAM Base Address Register
*/
mvebu_sdram_bs_set(bank, size);
}
+#if defined(CONFIG_ARCH_MVEBU)
+static u32 xor_ctrl_save;
+static u32 xor_base_save;
+static u32 xor_mask_save;
+
+static void mv_xor_init2(u32 cs)
+{
+ u32 reg, base, size, base2;
+ u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
+
+ xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
+ SCRB_XOR_CHAN));
+ xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
+ SCRB_XOR_WIN));
+ xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
+ SCRB_XOR_WIN));
+
+ /* Enable Window x for each CS */
+ reg = 0x1;
+ reg |= (0x3 << 16);
+ reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);
+
+ base = 0;
+ size = mvebu_sdram_bs(cs) - 1;
+ if (size) {
+ base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) |
+ bank_attr[cs];
+ reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
+ base2);
+
+ base += size + 1;
+ size = (size / (64 << 10)) << 16;
+ /* Window x - size - 256 MB */
+ reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
+ }
+
+ mv_xor_hal_init(0);
+
+ return;
+}
+
+static void mv_xor_finish2(void)
+{
+ reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
+ xor_ctrl_save);
+ reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
+ xor_base_save);
+ reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
+ xor_mask_save);
+}
+
+static void dram_ecc_scrubbing(void)
+{
+ int cs;
+ u32 size, temp;
+ u32 total_mem = 0;
+ u64 total;
+ u32 start_addr;
+
+ /*
+ * The DDR training code from the bin_hdr / SPL already
+ * scrubbed the DDR till 0x1000000. And the main U-Boot
+ * is loaded to an address < 0x1000000. So we need to
+ * skip this range to not re-scrub this area again.
+ */
+ temp = reg_read(REG_SDRAM_CONFIG_ADDR);
+ temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
+ reg_write(REG_SDRAM_CONFIG_ADDR, temp);
+
+ for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
+ size = mvebu_sdram_bs(cs) - 1;
+ if (size == 0)
+ continue;
+
+ total = (u64)size + 1;
+ total_mem += (u32)(total / (1 << 30));
+ start_addr = 0;
+ mv_xor_init2(cs);
+
+ /* Skip first 16 MiB */
+ if (0 == cs) {
+ start_addr = 0x1000000;
+ size -= start_addr;
+ }
+
+ mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size,
+ SCRUB_MAGIC, SCRUB_MAGIC);
+
+ /* Wait for previous transfer completion */
+ while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
+ ;
+
+ mv_xor_finish2();
+ }
+
+ temp = reg_read(REG_SDRAM_CONFIG_ADDR);
+ temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
+ reg_write(REG_SDRAM_CONFIG_ADDR, temp);
+}
+
+static int ecc_enabled(void)
+{
+ if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
+ return 1;
+
+ return 0;
+}
+#else
+static void dram_ecc_scrubbing(void)
+{
+}
+
+static int ecc_enabled(void)
+{
+ return 0;
+}
+#endif
+
int dram_init(void)
{
+ u64 size = 0;
int i;
- gd->ram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
- gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
/*
* It is assumed that all memory banks are consecutive
* and without gaps.
* If the gap is found, ram_size will be reported for
* consecutive memory only
*/
- if (gd->bd->bi_dram[i].start != gd->ram_size)
+ if (mvebu_sdram_bar(i) != size)
break;
/*
* Don't report more than 3GiB of SDRAM, otherwise there is no
* address space left for the internal registers etc.
*/
- if ((gd->ram_size + gd->bd->bi_dram[i].size != 0) &&
- (gd->ram_size + gd->bd->bi_dram[i].size <= (3 << 30)))
- gd->ram_size += gd->bd->bi_dram[i].size;
-
+ size += mvebu_sdram_bs(i);
+ if (size > SDRAM_SIZE_MAX)
+ size = SDRAM_SIZE_MAX;
}
for (; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].size = 0;
}
+
+ if (ecc_enabled())
+ dram_ecc_scrubbing();
+
+ gd->ram_size = size;
+
return 0;
}
* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
-void dram_init_banksize(void)
+int dram_init_banksize(void)
{
- dram_init();
+ u64 size = 0;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
+ gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
+
+ /* Clip the banksize to 1GiB if it exceeds the max size */
+ size += gd->bd->bi_dram[i].size;
+ if (size > SDRAM_SIZE_MAX)
+ mvebu_sdram_bs_set(i, 0x40000000);
+ }
+
+ return 0;
}
+#if defined(CONFIG_ARCH_MVEBU)
void board_add_ram_info(int use_default)
{
- u32 reg;
+ struct sar_freq_modes sar_freq;
+
+ get_sar_freq(&sar_freq);
+ printf(" (%d MHz, ", sar_freq.d_clk);
- reg = reg_read(REG_SDRAM_CONFIG_ADDR);
- if (reg & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
- printf(" (ECC");
+ if (ecc_enabled())
+ printf("ECC");
else
- printf(" (ECC not");
+ printf("ECC not");
printf(" enabled)");
}
+#endif
projects / u-boot / blobdiff