Merge branch 'next'

[u-boot] / arch / arm / mach-rockchip / rk3036 / sdram_rk3036.c

diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 7a05e310d73d10b94bd9f1cf732c5ace1065f596..ec8305cff82c5048f8456fb52c8a351e490e7ce4 100644 (file)
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -37,7 +37,7 @@ struct rk3036_sdram_priv {
 /* use integer mode, 396MHz dpll setting
  * refdiv, fbdiv, postdiv1, postdiv2
  */
-const struct pll_div dpll_init_cfg = {1, 66, 4, 1};
+const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
 
 /* 396Mhz ddr timing */
 const struct rk3036_ddr_timing ddr_timing = {0x18c,
@@ -701,15 +701,19 @@ finish:
 static void sdram_all_config(struct rk3036_sdram_priv *priv)
 {
        u32 os_reg = 0;
+       u32 cs1_row = 0;
        struct rk3036_ddr_config config = priv->ddr_config;
 
+       if (config.rank > 1)
+               cs1_row = config.cs1_row - 13;
+
        os_reg = config.ddr_type << DDR_TYPE_SHIFT |
                        0 << DDR_CHN_CNT_SHIFT |
                        (config.rank - 1) << DDR_RANK_CNT_SHIFT |
                        (config.col - 1) << DDR_COL_SHIFT |
                        (config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT |
                        (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT |
-                       (config.cs1_row - 13) << DDR_CS1_ROW_SHIFT |
+                       cs1_row << DDR_CS1_ROW_SHIFT |
                        1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT;
        writel(os_reg, &priv->grf->os_reg[1]);
 }