Merge git://git.denx.de/u-boot-rockchip

[u-boot] / arch / arm / mach-rockchip / rk3288 / sdram_rk3288.c

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index b36b6afcd978232ceedebc1479aa811d6d206fce..8020e9c6e2fb0a4572fda97002d4e1de8523e3d6 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -575,14 +575,14 @@ static void dram_all_config(const struct dram_info *dram,
                        &sdram_params->ch[chan];
 
                sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
-               sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
+               sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
                sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
                sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
-               sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
+               sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
                sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
                sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
-               sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
-               sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
+               sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+               sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
 
                dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
        }
@@ -734,13 +734,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
                rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
                        SYS_REG_RANK_MASK);
                col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
-               bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
+               bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
                cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
                                SYS_REG_CS0_ROW_MASK);
                cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
                                SYS_REG_CS1_ROW_MASK);
-               bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
-                       SYS_REG_BW_MASK;
+               bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+                       SYS_REG_BW_MASK));
                row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
                        SYS_REG_ROW_3_4_MASK;
 
@@ -755,10 +755,11 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
        }
 
        /*
-       * we use the 0x00000000~0xfeffffff space since 0xff000000~0xffffffff
-       * is SoC register space (i.e. reserved)
+       * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
+       * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is 
+       * inaccessible for some IP controller.
        */
-       size_mb = min(size_mb, 0xff000000 >> 20);
+       size_mb = min(size_mb, 0xfe000000 >> 20);
 
        return size_mb;
 }
@@ -784,7 +785,7 @@ static int veyron_init(struct dram_info *priv)
                return ret;
        udelay(100);/* Must wait for voltage to stabilize, 2mV/us */
 
-       rkclk_configure_cpu(priv->cru, priv->grf);
+       rk3288_clk_configure_cpu(priv->cru, priv->grf);
 
        return 0;
 }
@@ -923,7 +924,7 @@ static int rk3288_dmc_probe(struct udevice *dev)
        priv->chan[1].pctl = regmap_get_range(plat->map, 2);
        priv->chan[1].publ = regmap_get_range(plat->map, 3);
 #endif
-       ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
+       ret = rockchip_get_clk(&dev_clk);
        if (ret)
                return ret;
        priv->ddr_clk.id = CLK_DDR;