Merge git://git.denx.de/u-boot-fsl-qoriq

[u-boot] / arch / arm / mach-rockchip / rk3288 / sdram_rk3288.c

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 940ee58a642ccd9dd1b59c87ae6c8257c6eb291a..cf9ef2e8451aa9f2f6dca33953bf1f2be3a7f5b4 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
+#include <dt-structs.h>
 #include <errno.h>
 #include <ram.h>
 #include <regmap.h>
@@ -45,6 +46,9 @@ struct dram_info {
 };
 
 struct rk3288_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+       struct dtd_rockchip_rk3288_dmc of_plat;
+#endif
        struct rk3288_sdram_channel ch[2];
        struct rk3288_sdram_pctl_timing pctl_timing;
        struct rk3288_sdram_phy_timing phy_timing;
@@ -571,14 +575,14 @@ static void dram_all_config(const struct dram_info *dram,
                        &sdram_params->ch[chan];
 
                sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
-               sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
+               sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
                sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
                sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
-               sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
+               sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
                sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
                sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
-               sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
-               sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
+               sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+               sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
 
                dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
        }
@@ -730,13 +734,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
                rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
                        SYS_REG_RANK_MASK);
                col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
-               bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
+               bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
                cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
                                SYS_REG_CS0_ROW_MASK);
                cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
                                SYS_REG_CS1_ROW_MASK);
-               bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
-                       SYS_REG_BW_MASK;
+               bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+                       SYS_REG_BW_MASK));
                row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
                        SYS_REG_ROW_3_4_MASK;
 
@@ -780,7 +784,7 @@ static int veyron_init(struct dram_info *priv)
                return ret;
        udelay(100);/* Must wait for voltage to stabilize, 2mV/us */
 
-       rkclk_configure_cpu(priv->cru, priv->grf);
+       rk3288_clk_configure_cpu(priv->cru, priv->grf);
 
        return 0;
 }
@@ -806,6 +810,7 @@ static int setup_sdram(struct udevice *dev)
 
 static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
        struct rk3288_sdram_params *params = dev_get_platdata(dev);
        const void *blob = gd->fdt_blob;
        int node = dev->of_offset;
@@ -853,11 +858,39 @@ static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
        ret = regmap_init_mem(dev, &params->map);
        if (ret)
                return ret;
+#endif
 
        return 0;
 }
 #endif /* CONFIG_SPL_BUILD */
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
+{
+       struct rk3288_sdram_params *plat = dev_get_platdata(dev);
+       struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
+       int i, ret;
+
+       for (i = 0; i < 2; i++) {
+               memcpy(&plat->ch[i], of_plat->rockchip_sdram_channel,
+                      sizeof(plat->ch[i]));
+       }
+       memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
+              sizeof(plat->pctl_timing));
+       memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
+              sizeof(plat->phy_timing));
+       memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
+       plat->num_channels = of_plat->rockchip_num_channels;
+       ret = regmap_init_mem_platdata(dev, of_plat->reg,
+                                      ARRAY_SIZE(of_plat->reg) / 2,
+                                      &plat->map);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+#endif
+
 static int rk3288_dmc_probe(struct udevice *dev)
 {
 #ifdef CONFIG_SPL_BUILD
@@ -868,6 +901,11 @@ static int rk3288_dmc_probe(struct udevice *dev)
        int ret;
        struct udevice *dev_clk;
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+       ret = conv_of_platdata(dev);
+       if (ret)
+               return ret;
+#endif
        map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
        if (IS_ERR(map))
                return PTR_ERR(map);
@@ -885,7 +923,7 @@ static int rk3288_dmc_probe(struct udevice *dev)
        priv->chan[1].pctl = regmap_get_range(plat->map, 2);
        priv->chan[1].publ = regmap_get_range(plat->map, 3);
 #endif
-       ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
+       ret = rockchip_get_clk(&dev_clk);
        if (ret)
                return ret;
        priv->ddr_clk.id = CLK_DDR;
@@ -926,7 +964,7 @@ static const struct udevice_id rk3288_dmc_ids[] = {
 };
 
 U_BOOT_DRIVER(dmc_rk3288) = {
-       .name = "rk3288_dmc",
+       .name = "rockchip_rk3288_dmc",
        .id = UCLASS_RAM,
        .of_match = rk3288_dmc_ids,
        .ops = &rk3288_dmc_ops,