rockchip: reserve memory for rk3399 ATF data

[u-boot] / arch / arm / mach-rockchip / rk3288-board.c

diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index baf9522bcdd87a0ddc5e2bcd144beb83e588c764..9894a25e080f34daa5b574982a6dc6909068ca53 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -13,9 +13,12 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/periph.h>
 #include <asm/arch/pmu_rk3288.h>
+#include <asm/arch/qos_rk3288.h>
 #include <asm/arch/boot_mode.h>
 #include <asm/gpio.h>
 #include <dm/pinctrl.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -49,13 +52,65 @@ __weak int rk_board_late_init(void)
        return 0;
 }
 
+int rk3288_qos_init(void)
+{
+       int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
+       /* set vop qos to higher priority */
+       writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
+       writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
+
+       if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+                                      "rockchip,rk3288-tinker"))
+       {
+               /* set isp qos to higher priority */
+               writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
+               writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
+               writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
+       }
+       return 0;
+}
+
 int board_late_init(void)
 {
        setup_boot_mode();
+       rk3288_qos_init();
 
        return rk_board_late_init();
 }
 
+#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+static int veyron_init(void)
+{
+       struct udevice *dev;
+       struct clk clk;
+       int ret;
+
+       ret = regulator_get_by_platname("vdd_arm", &dev);
+       if (ret)
+               return ret;
+
+       /* Slowly raise to max CPU voltage to prevent overshoot */
+       ret = regulator_set_value(dev, 1200000);
+       if (ret)
+               return ret;
+       udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+       ret = regulator_set_value(dev, 1400000);
+       if (ret)
+               return ret;
+       udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+       ret = rockchip_get_clk(&clk.dev);
+       if (ret)
+               return ret;
+       clk.id = PLL_APLL;
+       ret = clk_set_rate(&clk, 1800000000);
+       if (IS_ERR_VALUE(ret))
+               return ret;
+
+       return 0;
+}
+#endif
+
 int board_init(void)
 {
 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
@@ -87,6 +142,15 @@ err:
 
        return -1;
 #else
+       int ret;
+
+       /* We do some SoC one time setting here */
+       if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+               ret = veyron_init();
+               if (ret)
+                       return ret;
+       }
+
        return 0;
 #endif
 }