rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL

[u-boot] / arch / arm / mach-rockchip / rk3288-board.c

diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 9894a25e080f34daa5b574982a6dc6909068ca53..d5f568c7932fe0501153361796a0e081ad1fd31e 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -78,7 +78,7 @@ int board_late_init(void)
        return rk_board_late_init();
 }
 
-#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 static int veyron_init(void)
 {
        struct udevice *dev;
@@ -86,8 +86,10 @@ static int veyron_init(void)
        int ret;
 
        ret = regulator_get_by_platname("vdd_arm", &dev);
-       if (ret)
+       if (ret) {
+               debug("Cannot set regulator name\n");
                return ret;
+       }
 
        /* Slowly raise to max CPU voltage to prevent overshoot */
        ret = regulator_set_value(dev, 1200000);
@@ -113,7 +115,7 @@ static int veyron_init(void)
 
 int board_init(void)
 {
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
        struct udevice *pinctrl;
        int ret;
 
@@ -155,28 +157,6 @@ err:
 #endif
 }
 
-int dram_init(void)
-{
-       struct ram_info ram;
-       struct udevice *dev;
-       int ret;
-
-       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-       if (ret) {
-               debug("DRAM init failed: %d\n", ret);
-               return ret;
-       }
-       ret = ram_get_info(dev, &ram);
-       if (ret) {
-               debug("Cannot get DRAM size: %d\n", ret);
-               return ret;
-       }
-       debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
-       gd->ram_size = ram.size;
-
-       return 0;
-}
-
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
@@ -307,3 +287,38 @@ U_BOOT_CMD(
        "display information about clocks",
        ""
 );
+
+#define GRF_SOC_CON2 0xff77024c
+
+int board_early_init_f(void)
+{
+       struct udevice *pinctrl;
+       struct udevice *dev;
+       int ret;
+
+       /*
+        * This init is done in SPL, but when chain-loading U-Boot SPL will
+        * have been skipped. Allow the clock driver to check if it needs
+        * setting up.
+        */
+       ret = rockchip_get_clk(&dev);
+       if (ret) {
+               debug("CLK init failed: %d\n", ret);
+               return ret;
+       }
+       ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+       if (ret) {
+               debug("%s: Cannot find pinctrl device\n", __func__);
+               return ret;
+       }
+
+       /* Enable debug UART */
+       ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+       if (ret) {
+               debug("%s: Failed to set up console UART\n", __func__);
+               return ret;
+       }
+       rk_setreg(GRF_SOC_CON2, 1 << 0);
+
+       return 0;
+}