rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL

[u-boot] / arch / arm / mach-rockchip / rk3399-board-spl.c

diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 4f84ec10a5662b2ae732097672e3c253e11e3c68..710f7feae218dbea14354034401ec258b86ec36d 100644 (file)
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -28,7 +28,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 static int spl_node_to_boot_device(int node)
 {
        struct udevice *parent;
@@ -156,19 +156,22 @@ void secure_timer_init(void)
        writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
 }
 
-#define GRF_EMMCCORE_CON11 0xff77f02c
-void board_init_f(ulong dummy)
+void board_debug_uart_init(void)
 {
-       struct udevice *pinctrl;
-       struct udevice *dev;
-       int ret;
-
-       /* Example code showing how to enable the debug UART on RK3288 */
 #include <asm/arch/grf_rk3399.h>
-       /* Enable early UART2 channel C on the RK3399 */
 #define GRF_BASE       0xff770000
        struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
 
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+       /* Enable early UART0 on the RK3399 */
+       rk_clrsetreg(&grf->gpio2c_iomux,
+                    GRF_GPIO2C0_SEL_MASK,
+                    GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
+       rk_clrsetreg(&grf->gpio2c_iomux,
+                    GRF_GPIO2C1_SEL_MASK,
+                    GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#else
+       /* Enable early UART2 channel C on the RK3399 */
        rk_clrsetreg(&grf->gpio4c_iomux,
                     GRF_GPIO4C3_SEL_MASK,
                     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
@@ -179,6 +182,18 @@ void board_init_f(ulong dummy)
        rk_clrsetreg(&grf->soc_con7,
                     GRF_UART_DBG_SEL_MASK,
                     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
+#endif
+}
+
+#define GRF_EMMCCORE_CON11 0xff77f02c
+#define SGRF_DDR_RGN_CON16 0xff330040
+#define SGRF_SLV_SECURE_CON4 0xff33e3d0
+void board_init_f(ulong dummy)
+{
+       struct udevice *pinctrl;
+       struct udevice *dev;
+       int ret;
+
 #define EARLY_UART
 #ifdef EARLY_UART
        /*
@@ -192,6 +207,7 @@ void board_init_f(ulong dummy)
        debug_uart_init();
        printascii("U-Boot SPL board init");
 #endif
+
        /*  Emmc clock generator: disable the clock multipilier */
        rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
 
@@ -201,6 +217,18 @@ void board_init_f(ulong dummy)
                hang();
        }
 
+       /*
+        * Disable DDR and SRAM security regions.
+        *
+        * As we are entered from the BootROM, the region from
+        * 0x0 through 0xfffff (i.e. the first MB of memory) will
+        * be protected. This will cause issues with the DW_MMC
+        * driver, which tries to DMA from/to the stack (likely)
+        * located in this range.
+        */
+       rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0);
+       rk_clrreg(SGRF_SLV_SECURE_CON4, 0x2000);
+
        secure_timer_init();
 
        ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
@@ -235,9 +263,10 @@ void spl_board_init(void)
        }
 
        preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
        back_to_bootrom();
 #endif
+
        return;
 err:
        printf("spl_board_init: Error %d\n", ret);