Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[u-boot] / arch / arm / mach-socfpga / Kconfig

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index dea4ce569f711844a3b41e53d37a432ee053efd0..d91b8bbcebc56c7dbd0622e1938d3d50e9b2dbb7 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,5 +1,32 @@
 if ARCH_SOCFPGA
 
+config SPL_LIBCOMMON_SUPPORT
+       default y
+
+config SPL_LIBDISK_SUPPORT
+       default y
+
+config SPL_LIBGENERIC_SUPPORT
+       default y
+
+config SPL_MMC_SUPPORT
+       default y if DM_MMC
+
+config SPL_NAND_SUPPORT
+       default y if SPL_NAND_DENALI
+
+config SPL_SERIAL_SUPPORT
+       default y
+
+config SPL_SPI_FLASH_SUPPORT
+       default y if SPL_SPI_SUPPORT
+
+config SPL_SPI_SUPPORT
+       default y if DM_SPI
+
+config SPL_WATCHDOG_SUPPORT
+       default y
+
 config TARGET_SOCFPGA_ARRIA5
        bool
        select TARGET_SOCFPGA_GEN5
@@ -27,14 +54,22 @@ config TARGET_SOCFPGA_DENX_MCVEVK
        bool "DENX MCVEVK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_SR1500
-       bool "SR1500 (Cyclone V)"
-       select TARGET_SOCFPGA_CYCLONE5
-
 config TARGET_SOCFPGA_EBV_SOCRATES
        bool "EBV SoCrates (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_IS1
+       bool "IS1 (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       bool "samtec VIN|ING FPGA (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SR1500
+       bool "SR1500 (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
        bool "Terasic DE0-Nano-Atlas (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -49,16 +84,19 @@ config SYS_BOARD
        default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+       default "is1" if TARGET_SOCFPGA_IS1
        default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
        default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "sr1500" if TARGET_SOCFPGA_SR1500
+       default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+       default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
@@ -69,9 +107,11 @@ config SYS_CONFIG_NAME
        default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+       default "socfpga_is1" if TARGET_SOCFPGA_IS1
        default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
        default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif