SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / arm / mach-socfpga / clock_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
index a23f3fc5d01fec3f0f141d521ab19a7b932004e4..3a64600861228e2b9d656e4d3cc50be8d2874561 100644 (file)
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -1,16 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/io.h>
+#include <dm.h>
 #include <asm/arch/clock_manager.h>
 #include <wait_bit.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 static const struct socfpga_clock_manager *clock_manager_base =
        (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
@@ -32,7 +30,7 @@ static void cm_write_ctrl(u32 val)
 }
 
 /* function to write a clock register that has phase information */
-static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
+static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
 {
        int ret;
 
@@ -267,26 +265,26 @@ int cm_basic_init(const struct cm_config * const cfg)
         * are aligned nicely; so we can change any phase.
         */
        ret = cm_write_with_phase(cfg->ddrdqsclk,
-                                 (u32)&clock_manager_base->sdr_pll.ddrdqsclk,
+                                 &clock_manager_base->sdr_pll.ddrdqsclk,
                                  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
        if (ret)
                return ret;
 
        /* SDRAM DDR2XDQSCLK */
        ret = cm_write_with_phase(cfg->ddr2xdqsclk,
-                                 (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk,
+                                 &clock_manager_base->sdr_pll.ddr2xdqsclk,
                                  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
        if (ret)
                return ret;
 
        ret = cm_write_with_phase(cfg->ddrdqclk,
-                                 (u32)&clock_manager_base->sdr_pll.ddrdqclk,
+                                 &clock_manager_base->sdr_pll.ddrdqclk,
                                  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
        if (ret)
                return ret;
 
        ret = cm_write_with_phase(cfg->s2fuser2clk,
-                                 (u32)&clock_manager_base->sdr_pll.s2fuser2clk,
+                                 &clock_manager_base->sdr_pll.s2fuser2clk,
                                  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
        if (ret)
                return ret;
@@ -507,6 +505,14 @@ unsigned int cm_get_spi_controller_clk_hz(void)
        return clock;
 }
 
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+       *rate = cm_get_spi_controller_clk_hz();
+
+       return 0;
+}
+
 void cm_print_clock_quick_summary(void)
 {
        printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);