arm: socfpga: Restructure FPGA driver in the preparation to support A10

[u-boot] / arch / arm / mach-socfpga / include / mach / fpga_manager.h

diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index a077e2284e65eb7642a41270a8237466f2d9133e..b046c2c437bd5fcf37ec5aa2d1cc4a6fb790e565 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  * All rights reserved.
  *
  * SPDX-License-Identifier:    BSD-3-Clause
@@ -10,58 +10,9 @@
 
 #include <altera.h>
 
-struct socfpga_fpga_manager {
-       /* FPGA Manager Module */
-       u32     stat;                   /* 0x00 */
-       u32     ctrl;
-       u32     dclkcnt;
-       u32     dclkstat;
-       u32     gpo;                    /* 0x10 */
-       u32     gpi;
-       u32     misci;                  /* 0x18 */
-       u32     _pad_0x1c_0x82c[517];
-
-       /* Configuration Monitor (MON) Registers */
-       u32     gpio_inten;             /* 0x830 */
-       u32     gpio_intmask;
-       u32     gpio_inttype_level;
-       u32     gpio_int_polarity;
-       u32     gpio_intstatus;         /* 0x840 */
-       u32     gpio_raw_intstatus;
-       u32     _pad_0x848;
-       u32     gpio_porta_eoi;
-       u32     gpio_ext_porta;         /* 0x850 */
-       u32     _pad_0x854_0x85c[3];
-       u32     gpio_1s_sync;           /* 0x860 */
-       u32     _pad_0x864_0x868[2];
-       u32     gpio_ver_id_code;
-       u32     gpio_config_reg2;       /* 0x870 */
-       u32     gpio_config_reg1;
-};
-
-#define FPGAMGRREGS_STAT_MODE_MASK             0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK             0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB              3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK          0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK         0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK      0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK              0x2
-#define FPGAMGRREGS_CTRL_EN_MASK               0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB           6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK        0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF               0x0
-#define FPGAMGRREGS_MODE_RESETPHASE            0x1
-#define FPGAMGRREGS_MODE_CFGPHASE              0x2
-#define FPGAMGRREGS_MODE_INITPHASE             0x3
-#define FPGAMGRREGS_MODE_USERMODE              0x4
-#define FPGAMGRREGS_MODE_UNKNOWN               0x5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/fpga_manager_gen5.h>
+#endif
 
 /* FPGA CD Ratio Value */
 #define CDRATIO_x1                             0x0
@@ -69,9 +20,14 @@ struct socfpga_fpga_manager {
 #define CDRATIO_x4                             0x2
 #define CDRATIO_x8                             0x3
 
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
 int fpgamgr_get_mode(void);
+int fpgamgr_poll_fpga_ready(void);
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_dclkcnt_set(unsigned long cnt);
 
+#endif /* __ASSEMBLY__ */
 #endif /* _FPGA_MANAGER_H_ */