#endif
}
+void v7_outer_cache_enable(void)
+{
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+ /* enable BRESP, instruction and data prefetch, full line of zeroes */
+ setbits_le32(&pl310->pl310_aux_ctrl,
+ L310_AUX_CTRL_DATA_PREFETCH_MASK |
+ L310_AUX_CTRL_INST_PREFETCH_MASK |
+ L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ /* Enable the L2 cache */
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
/*
* DesignWare Ethernet initialization
*/
}
#endif
-#ifdef CONFIG_DWMMC
-/*
- * Initializes MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
-/*
- * FIXME: Temporarily define CONFIG_HPS_SDMMC_BUSWIDTH to prevent breakage
- * due to missing patches in u-boot/master . The upcoming patch will
- * switch this to OF probing, so this whole block will go away.
- */
-#define CONFIG_HPS_SDMMC_BUSWIDTH 8
- return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
- CONFIG_HPS_SDMMC_BUSWIDTH, 0);
-}
-#endif
-
struct {
const char *mode;
const char *name;
socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
#endif
+#ifdef CONFIG_NAND_DENALI
+ socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
+
return 0;
}