arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

[u-boot] / arch / arm / mach-socfpga / misc.c

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 0940cc5a4ff3f684e8b7882d53f496c8955a73a3..bbd31ef7b522dcd6bab0ff445f6ba3da0c69e097 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -52,6 +52,18 @@ void enable_caches(void)
 #endif
 }
 
+void v7_outer_cache_enable(void)
+{
+       /* disable the L2 cache */
+       writel(0, &pl310->pl310_ctrl);
+
+       /* enable BRESP, instruction and data prefetch, full line of zeroes */
+       setbits_le32(&pl310->pl310_aux_ctrl,
+                    L310_AUX_CTRL_DATA_PREFETCH_MASK |
+                    L310_AUX_CTRL_INST_PREFETCH_MASK |
+                    L310_SHARED_ATT_OVERRIDE_ENABLE);
+}
+
 /*
  * DesignWare Ethernet initialization
  */