ti: AM335x: Use generic EEPROM detection logic

[u-boot] / arch / arm / mach-socfpga / misc.c

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index bbd31ef7b522dcd6bab0ff445f6ba3da0c69e097..ce3ff0acc4d38f558b21b49fc8b23463630b988d 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -54,14 +54,23 @@ void enable_caches(void)
 
 void v7_outer_cache_enable(void)
 {
-       /* disable the L2 cache */
-       writel(0, &pl310->pl310_ctrl);
+       /* Disable the L2 cache */
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
        /* enable BRESP, instruction and data prefetch, full line of zeroes */
        setbits_le32(&pl310->pl310_aux_ctrl,
                     L310_AUX_CTRL_DATA_PREFETCH_MASK |
                     L310_AUX_CTRL_INST_PREFETCH_MASK |
                     L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+       /* Enable the L2 cache */
+       setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+       /* Disable the L2 cache */
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
 
 /*
@@ -95,7 +104,7 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id)
        socfpga_per_reset(reset, 0);
 }
 
-int cpu_eth_init(bd_t *bis)
+static int socfpga_eth_reset(void)
 {
        const void *fdt = gd->fdt_blob;
        struct fdtdec_phandle_args args;
@@ -128,17 +137,11 @@ int cpu_eth_init(bd_t *bis)
 
        return 0;
 }
-#endif
-
-#ifdef CONFIG_DWMMC
-/*
- * Initializes MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
+#else
+static int socfpga_eth_reset(void)
 {
-       return socfpga_dwmmc_init(gd->fdt_blob);
-}
+       return 0
+};
 #endif
 
 struct {
@@ -234,7 +237,7 @@ int arch_misc_init(void)
        setenv("bootmode", bsel_str[bsel].mode);
        if (fpga_id >= 0)
                setenv("fpgatype", socfpga_fpga_model[fpga_id].var);
-       return 0;
+       return socfpga_eth_reset();
 }
 #endif
 
@@ -361,6 +364,10 @@ int arch_early_init_r(void)
        socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 #endif
 
+#ifdef CONFIG_NAND_DENALI
+       socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
+
        return 0;
 }