Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

[u-boot] / arch / arm / mach-socfpga / reset_manager.c

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 6a11c19200d7c72d94e3706627096e2d2573d00a..b6beaa2f220439a1f5d1c66a1780d2087a4c5f2a 100644 (file)
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -7,13 +7,16 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/reset_manager.h>
 #include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_reset_manager *reset_manager_base =
                (void *)SOCFPGA_RSTMGR_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
@@ -39,6 +42,19 @@ void socfpga_per_reset(u32 reset, int set)
                clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
 }
 
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+       const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+       writel(~l4wd0, &reset_manager_base->per_mod_reset);
+       writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+}
+
 /*
  * Write the reset manager register to cause reset
  */
@@ -84,6 +100,9 @@ void socfpga_bridges_reset(int enable)
                /* brdmodrst */
                writel(0xffffffff, &reset_manager_base->brg_mod_reset);
        } else {
+               writel(0, &sysmgr_regs->iswgrp_handoff[0]);
+               writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
+
                /* Check signal from FPGA. */
                if (!fpgamgr_test_fpga_ready()) {
                        /* FPGA not ready, do nothing. */