arm: socfpga: spl: Merge spl_board_init() into board_init_f()

[u-boot] / arch / arm / mach-socfpga / spl.c

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 15fee0ad97b9234f4a55eff36384ecb1861b9b39..ea0ed1a24d7fd18fbcc63658b52262f1f82f8508 100644 (file)
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -29,6 +29,11 @@ static struct scu_registers *scu_regs =
 static struct nic301_registers *nic301_regs =
        (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 
+u32 spl_boot_device(void)
+{
+       return BOOT_DEVICE_RAM;
+}
+
 static void socfpga_nic301_slave_ns(void)
 {
        writel(0x1, &nic301_regs->lwhps2fpgaregs);
@@ -41,9 +46,14 @@ static void socfpga_nic301_slave_ns(void)
 
 void board_init_f(ulong dummy)
 {
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+       const struct cm_config *cm_default_cfg = cm_get_default_config();
+#endif
        struct socfpga_system_manager *sysmgr_regs =
                (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+       unsigned long sdram_size;
        unsigned long reg;
+
        /*
         * First C code to run. Clear fake OCRAM ECC first as SBE
         * and DBE might triggered during power on
@@ -67,28 +77,16 @@ void board_init_f(ulong dummy)
        writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
        writel(0x1, &pl310->pl310_addr_filter_start);
 
-       board_init_r(NULL, 0);
-}
-
-u32 spl_boot_device(void)
-{
-       return BOOT_DEVICE_RAM;
-}
-
-/*
- * Board initialization after bss clearance
- */
-void spl_board_init(void)
-{
-       unsigned long sdram_size;
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
-       const struct cm_config *cm_default_cfg = cm_get_default_config();
-#endif
-
        debug("Freezing all I/O banks\n");
        /* freeze all IO banks */
        sys_mgr_frzctrl_freeze_req();
 
+       /* Put everything into reset but L4WD0. */
+       socfpga_per_reset_all();
+       /* Put FPGA bridges into reset too. */
+       socfpga_bridges_reset(1);
+
        socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
        socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
        socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
@@ -115,8 +113,9 @@ void spl_board_init(void)
 
 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 
-       /* de-assert reset for peripherals and bridges based on handoff */
+       /* De-assert reset for peripherals and bridges based on handoff */
        reset_deassert_peripherals_handoff();
+       socfpga_bridges_reset(0);
 
        debug("Unfreezing/Thaw all I/O banks\n");
        /* unfreeze / thaw all IO banks */
@@ -145,4 +144,8 @@ void spl_board_init(void)
                puts("SDRAM size check failed!\n");
                hang();
        }
+
+       socfpga_bridges_reset(1);
+
+       board_init_r(NULL, 0);
 }