stm32f7: add support for stm32f769 disco board

[u-boot] / arch / arm / mach-stm32 / stm32f4 / clock.c

diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c
index 3deb17aa833a6a3f18bab2e2cc2c53a12f91b558..15fcadbbe6fa162b728c19e7e7ae32415ff9fdcf 100644 (file)
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/stm32.h>
+#include <asm/arch/stm32_periph.h>
 
 #define RCC_CR_HSION           (1 << 0)
 #define RCC_CR_HSEON           (1 << 16)
@@ -50,6 +51,14 @@
 
 #define RCC_APB1ENR_PWREN      (1 << 28)
 
+/*
+ * RCC USART specific definitions
+ */
+#define RCC_ENR_USART1EN               (1 << 4)
+#define RCC_ENR_USART2EN               (1 << 17)
+#define RCC_ENR_USART3EN               (1 << 18)
+#define RCC_ENR_USART6EN               (1 <<  5)
+
 #define PWR_CR_VOS0            (1 << 14)
 #define PWR_CR_VOS1            (1 << 15)
 #define PWR_CR_VOS_MASK                0xC000
@@ -57,10 +66,20 @@
 #define PWR_CR_VOS_SCALE_MODE_2        (PWR_CR_VOS1)
 #define PWR_CR_VOS_SCALE_MODE_3        (PWR_CR_VOS0)
 
-#define FLASH_ACR_WS(n)                n
-#define FLASH_ACR_PRFTEN       (1 << 8)
-#define FLASH_ACR_ICEN         (1 << 9)
-#define FLASH_ACR_DCEN         (1 << 10)
+/*
+ * RCC GPIO specific definitions
+ */
+#define RCC_ENR_GPIO_A_EN      (1 << 0)
+#define RCC_ENR_GPIO_B_EN      (1 << 1)
+#define RCC_ENR_GPIO_C_EN      (1 << 2)
+#define RCC_ENR_GPIO_D_EN      (1 << 3)
+#define RCC_ENR_GPIO_E_EN      (1 << 4)
+#define RCC_ENR_GPIO_F_EN      (1 << 5)
+#define RCC_ENR_GPIO_G_EN      (1 << 6)
+#define RCC_ENR_GPIO_H_EN      (1 << 7)
+#define RCC_ENR_GPIO_I_EN      (1 << 8)
+#define RCC_ENR_GPIO_J_EN      (1 << 9)
+#define RCC_ENR_GPIO_K_EN      (1 << 10)
 
 struct pll_psc {
        u8      pll_m;
@@ -157,10 +176,7 @@ int configure_clocks(void)
        while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
                ;
 
-       /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
-       writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
-               | FLASH_ACR_DCEN, &STM32_FLASH->acr);
-
+       stm32_flash_latency_cfg(5);
        clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
        setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
 
@@ -221,3 +237,47 @@ unsigned long clock_get(enum clock clck)
                break;
        }
 }
+
+void clock_setup(int peripheral)
+{
+       switch (peripheral) {
+       case USART1_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
+               break;
+       case GPIO_A_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
+               break;
+       case GPIO_B_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
+               break;
+       case GPIO_C_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
+               break;
+       case GPIO_D_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
+               break;
+       case GPIO_E_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
+               break;
+       case GPIO_F_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
+               break;
+       case GPIO_G_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
+               break;
+       case GPIO_H_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
+               break;
+       case GPIO_I_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
+               break;
+       case GPIO_J_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
+               break;
+       case GPIO_K_CLOCK_CFG:
+               setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
+               break;
+       default:
+               break;
+       }
+}