stm32: Correct positioning of declaration

[u-boot] / arch / arm / mach-stm32 / stm32f7 / soc.c

diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c
index 6f9704ab78853cdab55ee4a65bcc2adf18abf466..a960cc1cbfdac7fd9931fc067bf181edced56874 100644 (file)
--- a/arch/arm/mach-stm32/stm32f7/soc.c
+++ b/arch/arm/mach-stm32/stm32f7/soc.c
@@ -7,7 +7,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/armv7m.h>
+#include <asm/armv7m_mpu.h>
 #include <asm/arch/stm32.h>
 
 u32 get_cpu_rev(void)
@@ -17,56 +17,29 @@ u32 get_cpu_rev(void)
 
 int arch_cpu_init(void)
 {
-       /*
-               * Configure the memory protection unit (MPU)
-               * 0x00000000 - 0xffffffff: Strong-order, Shareable
-               * 0xC0000000 - 0xC0800000: Normal, Outer and inner Non-cacheable
-        */
+       int i;
 
-        /* Disable MPU */
-        writel(0, &V7M_MPU->ctrl);
+       struct mpu_region_config stm32_region_config[] = {
+               { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+               O_I_WB_RD_WR_ALLOC, REGION_4GB },
 
-        writel(
-                0x00000000 /* address */
-                | 1 << 4       /* VALID */
-                | 0 << 0       /* REGION */
-                , &V7M_MPU->rbar
-        );
+               { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+               STRONG_ORDER, REGION_512MB },
 
-        /* Strong-order, Shareable */
-        /* TEX=000, S=1, C=0, B=0*/
-        writel(
-                (V7M_MPU_RASR_XN_ENABLE
-                        | V7M_MPU_RASR_AP_RW_RW
-                        | 0x01 << V7M_MPU_RASR_S_SHIFT
-                        | 0x00 << V7M_MPU_RASR_TEX_SHIFT
-                        | V7M_MPU_RASR_SIZE_4GB
-                        | V7M_MPU_RASR_EN)
-                , &V7M_MPU->rasr
-        );
+               { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
+               DEVICE_NON_SHARED, REGION_512MB },
 
-        writel(
-                0xC0000000 /* address */
-                | 1 << 4       /* VALID */
-                | 1 << 0       /* REGION */
-                , &V7M_MPU->rbar
-        );
+               { 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
+               DEVICE_NON_SHARED, REGION_512MB },
 
-        /* Normal, Outer and inner Non-cacheable */
-        /* TEX=001, S=0, C=0, B=0*/
-        writel(
-                (V7M_MPU_RASR_XN_ENABLE
-                        | V7M_MPU_RASR_AP_RW_RW
-                        | 0x01 << V7M_MPU_RASR_TEX_SHIFT
-                        | 0x01 << V7M_MPU_RASR_B_SHIFT
-                        | 0x01 << V7M_MPU_RASR_C_SHIFT
-                        | V7M_MPU_RASR_SIZE_8MB
-                        | V7M_MPU_RASR_EN)
-                        , &V7M_MPU->rasr
-        );
+               { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
+               STRONG_ORDER, REGION_512MB },
+       };
 
-        /* Enable MPU */
-        writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
+       disable_mpu();
+       for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
+               mpu_config(&stm32_region_config[i]);
+       enable_mpu();
 
        return 0;
 }