sunxi: prepare for sharing MACH_SUN8I_H3 config symbol

[u-boot] / arch / arm / mach-sunxi / board.c

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 6d9518d4c6036a09a7462674df5ef0a940404ef6..5e03d039433a06b8edb96371a865f6d76395ec01 100644 (file)
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -40,7 +40,7 @@ struct fel_stash {
 
 struct fel_stash fel_stash __attribute__((section(".data")));
 
-#ifdef CONFIG_MACH_SUN50I
+#ifdef CONFIG_ARM64
 #include <asm/armv8/mmu.h>
 
 static struct mm_region sunxi_mem_map[] = {
@@ -98,7 +98,7 @@ static int gpio_init(void)
        sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
        sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
        sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
        sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
@@ -133,13 +133,17 @@ static int gpio_init(void)
        return 0;
 }
 
-int spl_board_load_image(void)
+#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
+static int spl_board_load_image(struct spl_image_info *spl_image,
+                               struct spl_boot_device *bootdev)
 {
        debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
        return_to_fel(fel_stash.sp, fel_stash.lr);
 
        return 0;
 }
+SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+#endif
 
 void s_init(void)
 {
@@ -176,14 +180,13 @@ void s_init(void)
        /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
 #endif
 
-#if defined CONFIG_MACH_SUN6I || \
-    defined CONFIG_MACH_SUN7I || \
-    defined CONFIG_MACH_SUN8I
+#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
        /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
        asm volatile(
                "mrc p15, 0, r0, c1, c0, 1\n"
                "orr r0, r0, #1 << 6\n"
-               "mcr p15, 0, r0, c1, c0, 1\n");
+               "mcr p15, 0, r0, c1, c0, 1\n"
+               ::: "r0");
 #endif
 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
        /* Enable non-secure access to some peripherals */
@@ -242,15 +245,6 @@ u32 spl_boot_device(void)
        return -1;              /* Never reached */
 }
 
-/*
- * Properly announce BOOT_DEVICE_BOARD as "FEL".
- * Overrides weak function from common/spl/spl.c
- */
-void spl_board_announce_boot_device(void)
-{
-       printf("FEL");
-}
-
 /* No confirmation data available in SPL yet. Hardcode bootmode */
 u32 spl_boot_mode(const u32 boot_device)
 {