SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / arm / mach-sunxi / board.c

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 58fbacb774cb7e136a3a7f0fe6304482f63a6bbb..7ac8360c0117a824fc17c606f3e5f563fd6a585a 100644 (file)
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  *
@@ -6,17 +7,13 @@
  * Tom Cubie <tangliang@allwinnertech.com>
  *
  * Some init for sunxi platform.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <mmc.h>
 #include <i2c.h>
 #include <serial.h>
-#ifdef CONFIG_SPL_BUILD
 #include <spl.h>
-#endif
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -40,7 +37,7 @@ struct fel_stash {
 
 struct fel_stash fel_stash __attribute__((section(".data")));
 
-#ifdef CONFIG_MACH_SUN50I
+#ifdef CONFIG_ARM64
 #include <asm/armv8/mmu.h>
 
 static struct mm_region sunxi_mem_map[] = {
@@ -69,12 +66,14 @@ struct mm_region *mem_map = sunxi_mem_map;
 static int gpio_init(void)
 {
 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || \
+    defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
        /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
        sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
 #endif
-#if defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
        sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
 #else
@@ -82,7 +81,9 @@ static int gpio_init(void)
        sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
 #endif
        sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
-#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
+                                defined(CONFIG_MACH_SUN7I) || \
+                                defined(CONFIG_MACH_SUN8I_R40))
        sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
        sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
@@ -98,7 +99,7 @@ static int gpio_init(void)
        sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
        sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
        sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
        sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
@@ -110,6 +111,10 @@ static int gpio_init(void)
        sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
        sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
+       sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
        sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
@@ -180,10 +185,7 @@ void s_init(void)
        /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
 #endif
 
-#if defined CONFIG_MACH_SUN6I || \
-    defined CONFIG_MACH_SUN7I || \
-    defined CONFIG_MACH_SUN8I || \
-    defined CONFIG_MACH_SUN9I
+#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
        /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
        asm volatile(
                "mrc p15, 0, r0, c1, c0, 1\n"
@@ -199,17 +201,19 @@ void s_init(void)
        clock_init();
        timer_init();
        gpio_init();
+#ifndef CONFIG_DM_I2C
        i2c_init_board();
+#endif
        eth_init_board();
 }
 
 #ifdef CONFIG_SPL_BUILD
-DECLARE_GLOBAL_DATA_PTR;
+#endif
 
 /* The sunxi internal brom will try to loader external bootloader
  * from mmc0, nand flash, mmc2.
  */
-u32 spl_boot_device(void)
+uint32_t sunxi_get_boot_device(void)
 {
        int boot_source;
 
@@ -248,10 +252,10 @@ u32 spl_boot_device(void)
        return -1;              /* Never reached */
 }
 
-/* No confirmation data available in SPL yet. Hardcode bootmode */
-u32 spl_boot_mode(const u32 boot_device)
+#ifdef CONFIG_SPL_BUILD
+u32 spl_boot_device(void)
 {
-       return MMCSD_MODE_RAW;
+       return sunxi_get_boot_device();
 }
 
 void board_init_f(ulong dummy)
@@ -269,7 +273,7 @@ void board_init_f(ulong dummy)
 
 void reset_cpu(ulong addr)
 {
-#ifdef CONFIG_SUNXI_GEN_SUN4I
+#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
        static const struct sunxi_wdog *wdog =
                 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 
@@ -281,8 +285,7 @@ void reset_cpu(ulong addr)
                /* sun5i sometimes gets stuck without this */
                writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
        }
-#endif
-#ifdef CONFIG_SUNXI_GEN_SUN6I
+#elif defined(CONFIG_SUNXI_GEN_SUN6I)
        static const struct sunxi_wdog *wdog =
                 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;