Merge branch 'master' of git://git.denx.de/u-boot-tegra

[u-boot] / arch / arm / mach-tegra / board.c

diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index 87511a31df180526225b14efa9288e80013f6f77..222de6a7352d4420bcf38f5cdeb8cbef406cb66d 100644 (file)
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -11,6 +11,7 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/mc.h>
 #include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/sys_proto.h>
@@ -28,6 +29,24 @@ enum {
        UART_COUNT = 5,
 };
 
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+#if !defined(CONFIG_TEGRA124)
+#error tegra_cpu_is_non_secure has only been validated on Tegra124
+#endif
+bool tegra_cpu_is_non_secure(void)
+{
+       /*
+        * This register reads 0xffffffff in non-secure mode. This register
+        * only implements bits 31:20, so the lower bits will always read 0 in
+        * secure mode. Thus, the lower bits are an indicator for secure vs.
+        * non-secure mode.
+        */
+       struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+       uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
+       return (mc_s_cfg0 & 1) == 1;
+}
+#endif
+
 /* Read the RAM size directly from the memory controller */
 unsigned int query_sdram_size(void)
 {
@@ -79,14 +98,6 @@ int dram_init(void)
        return 0;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-       printf("Board: %s\n", sysinfo.board_string);
-       return 0;
-}
-#endif /* CONFIG_DISPLAY_BOARDINFO */
-
 static int uart_configs[] = {
 #if defined(CONFIG_TEGRA20)
  #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)