arm: ls1021atwr: Convert to driver model and enable serial support

[u-boot] / arch / arm / mach-tegra / board.c

diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index 40de72dc575fd1a84d097461edeb251fa04c12b5..3d1d26d13d1399b38b1fadac66721a8bb4c08e2e 100644 (file)
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -6,6 +6,8 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <ns16550.h>
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -66,10 +68,11 @@ bool tegra_cpu_is_non_secure(void)
 #endif
 
 /* Read the RAM size directly from the memory controller */
-unsigned int query_sdram_size(void)
+static phys_size_t query_sdram_size(void)
 {
        struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
-       u32 emem_cfg, size_bytes;
+       u32 emem_cfg;
+       phys_size_t size_bytes;
 
        emem_cfg = readl(&mc->mc_emem_cfg);
 #if defined(CONFIG_TEGRA20)
@@ -77,6 +80,7 @@ unsigned int query_sdram_size(void)
        size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
 #else
        debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
+#ifndef CONFIG_PHYS_64BIT
        /*
         * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
         * and will wrap. Clip the reported size to the maximum that a 32-bit
@@ -84,9 +88,12 @@ unsigned int query_sdram_size(void)
         */
        if (emem_cfg >= 4096) {
                size_bytes = U32_MAX & ~(0x1000 - 1);
-       } else {
+       } else
+#endif
+       {
                /* RAM size EMC is programmed to. */
-               size_bytes = emem_cfg * 1024 * 1024;
+               size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
+#ifndef CONFIG_ARM64
                /*
                 * If all RAM fits within 32-bits, it can be accessed without
                 * LPAE, so go test the RAM size. Otherwise, we can't access
@@ -97,6 +104,7 @@ unsigned int query_sdram_size(void)
                if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
                        size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
                                                  size_bytes);
+#endif
        }
 #endif
 
@@ -206,6 +214,18 @@ void board_init_uart_f(void)
        setup_uarts(uart_ids);
 }
 
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static struct ns16550_platdata ns16550_com1_pdata = {
+       .base = CONFIG_SYS_NS16550_COM1,
+       .reg_shift = 2,
+       .clock = CONFIG_SYS_NS16550_CLK,
+};
+
+U_BOOT_DEVICE(ns16550_com1) = {
+       "ns16550_serial", &ns16550_com1_pdata
+};
+#endif
+
 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 void enable_caches(void)
 {