return 0;
}
+static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
+{
+ u32 *reg = get_periph_source_reg(periph_id);
+ u32 val = readl(reg);
+
+ switch (mux_bits) {
+ case MASK_BITS_31_30:
+ val >>= OUT_CLK_SOURCE_31_30_SHIFT;
+ val &= OUT_CLK_SOURCE_31_30_MASK;
+ return val;
+ case MASK_BITS_31_29:
+ val >>= OUT_CLK_SOURCE_31_29_SHIFT;
+ val &= OUT_CLK_SOURCE_31_29_MASK;
+ return val;
+ case MASK_BITS_31_28:
+ val >>= OUT_CLK_SOURCE_31_28_SHIFT;
+ val &= OUT_CLK_SOURCE_31_28_MASK;
+ return val;
+ default:
+ return -1;
+ }
+}
+
void clock_ll_set_source(enum periph_id periph_id, unsigned source)
{
clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
return 0;
}
+enum clock_id clock_get_periph_parent(enum periph_id periph_id)
+{
+ int err, mux_bits, divider_bits, type;
+ int source;
+
+ err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type);
+ if (err)
+ return CLOCK_ID_NONE;
+
+ source = clock_ll_get_source_bits(periph_id, mux_bits);
+
+ return get_periph_clock_id(periph_id, source);
+}
+
unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
enum clock_id parent, unsigned rate, int *extra_div)
{
void clock_init(void)
{
+ int i;
+
pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
+
+ for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
+ enum periph_id periph_id;
+ enum clock_id parent;
+ int source, mux_bits, divider_bits;
+
+ periph_id = periph_clk_init_table[i].periph_id;
+ parent = periph_clk_init_table[i].parent_clock_id;
+
+ source = get_periph_clock_source(periph_id, parent, &mux_bits,
+ ÷r_bits);
+ clock_ll_set_source_bits(periph_id, mux_bits, source);
+ }
}
static void set_avp_clock_source(u32 src)