Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[u-boot] / arch / arm / mach-tegra / tegra124 / clock.c

diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 912621863a206f8ebaf670b4ea4e04d2263be770..1e71146236e9d3dd52052248ef9751f6c7aaa686 100644 (file)
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -570,7 +570,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
  */
 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
        /*
-        * T124: same as T114, some deviations from T2x/T30.
+        * T124: same as T114, some deviations from T2x/T30. Adds PLLDP.
         * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
         *       If lock_ena or lock_det are >31, they're not used in that PLL.
         */
@@ -593,6 +593,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
          .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },     /* PLLE */
        { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
          .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
+       { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20,  .p_mask = 0xF,
+         .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 },   /* PLLDP */
 };
 
 /*
@@ -730,7 +732,7 @@ void reset_set_enable(enum periph_id periph_id, int enable)
        writel(reg, reset);
 }
 
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 /*
  * Convert a device tree clock ID to our peripheral ID. They are mostly
  * the same but we are very cautious so we check that a valid clock ID is
@@ -796,7 +798,7 @@ enum periph_id clk_id_to_periph_id(int clk_id)
                return clk_id;
        }
 }
-#endif /* CONFIG_OF_CONTROL */
+#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
 
 void clock_early_init(void)
 {
@@ -807,6 +809,11 @@ void clock_early_init(void)
 
        tegra30_set_up_pllp();
 
+       /* clear IDDQ before accessing any other PLLC registers */
+       pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
+       clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
+       udelay(2);
+
        /*
         * PLLC output frequency set to 600Mhz
         * PLLD output frequency set to 925Mhz
@@ -857,8 +864,8 @@ void arch_timer_init(void)
        struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
        u32 freq, val;
 
-       freq = clock_get_rate(CLOCK_ID_OSC);
-       debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+       freq = clock_get_rate(CLOCK_ID_CLK_M);
+       debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
 
        /* ARM CNTFRQ */
        asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));