SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / arm / mach-tegra / tegra20 / clock.c

diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index d11e89bd253f08097e4f61b4552398fb860f34a7..8f1bb4f069ddb056e119a96d8c7ae30a164ea71b 100644 (file)
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
  * (C) Copyright 2010-2015
  * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* Tegra20 Clock control functions */
@@ -413,46 +412,78 @@ u32 *get_periph_source_reg(enum periph_id periph_id)
        return &clkrst->crc_clk_src[internal_id];
 }
 
-/**
- * Given a peripheral ID and the required source clock, this returns which
- * value should be programmed into the source mux for that peripheral.
- *
- * There is special code here to handle the one source type with 5 sources.
- *
- * @param periph_id    peripheral to start
- * @param source       PLL id of required parent clock
- * @param mux_bits     Set to number of bits in mux register: 2 or 4
- * @param divider_bits Set to number of divider bits (8 or 16)
- * @return mux value (0-4, or -1 if not found)
- */
-int get_periph_clock_source(enum periph_id periph_id,
-               enum clock_id parent, int *mux_bits, int *divider_bits)
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+                         int *divider_bits, int *type)
 {
-       enum clock_type_id type;
        enum periphc_internal_id internal_id;
-       int mux;
 
-       assert(clock_periph_id_isvalid(periph_id));
+       if (!clock_periph_id_isvalid(periph_id))
+               return -1;
 
        internal_id = periph_id_to_internal_id[periph_id];
-       assert(periphc_internal_id_isvalid(internal_id));
+       if (!periphc_internal_id_isvalid(internal_id))
+               return -1;
 
-       type = clock_periph_type[internal_id];
-       assert(clock_type_id_isvalid(type));
+       *type = clock_periph_type[internal_id];
+       if (!clock_type_id_isvalid(*type))
+               return -1;
 
        /*
         * Special cases here for the clock with a 4-bit source mux and I2C
         * with its 16-bit divisor
         */
-       if (type == CLOCK_TYPE_PCXTS)
+       if (*type == CLOCK_TYPE_PCXTS)
                *mux_bits = MASK_BITS_31_28;
        else
                *mux_bits = MASK_BITS_31_30;
-       if (type == CLOCK_TYPE_PCMT16)
+       if (*type == CLOCK_TYPE_PCMT16)
                *divider_bits = 16;
        else
                *divider_bits = 8;
 
+       return 0;
+}
+
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
+{
+       enum periphc_internal_id internal_id;
+       int type;
+
+       if (!clock_periph_id_isvalid(periph_id))
+               return CLOCK_ID_NONE;
+
+       internal_id = periph_id_to_internal_id[periph_id];
+       if (!periphc_internal_id_isvalid(internal_id))
+               return CLOCK_ID_NONE;
+
+       type = clock_periph_type[internal_id];
+       if (!clock_type_id_isvalid(type))
+               return CLOCK_ID_NONE;
+
+       return clock_source[type][source];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id    peripheral to start
+ * @param source       PLL id of required parent clock
+ * @param mux_bits     Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+               enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+       enum clock_type_id type;
+       int mux, err;
+
+       err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
+       assert(!err);
+
        for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
                if (clock_source[type][mux] == parent)
                        return mux;
@@ -635,7 +666,7 @@ static int tegra_plle_train(void)
        } while (--timeout);
 
        if (timeout == 0) {
-               error("timeout waiting for PLLE to become ready");
+               pr_err("timeout waiting for PLLE to become ready");
                return -ETIMEDOUT;
        }
 
@@ -665,7 +696,7 @@ int tegra_plle_enable(void)
        if ((value & PLLE_MISC_PLL_READY) == 0) {
                err = tegra_plle_train();
                if (err < 0) {
-                       error("failed to train PLLE: %d", err);
+                       pr_err("failed to train PLLE: %d", err);
                        return err;
                }
        }
@@ -694,7 +725,7 @@ int tegra_plle_enable(void)
        } while (--timeout);
 
        if (timeout == 0) {
-               error("timeout waiting for PLLE to lock");
+               pr_err("timeout waiting for PLLE to lock");
                return -ETIMEDOUT;
        }