Merge branch 'master' of git://git.denx.de/u-boot-socfpga

[u-boot] / arch / arm / mach-tegra / tegra20 / clock.c

diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index cd9fb9a55340ffa5b29a0633a2b248243fa1b08a..ec04cf5261f7ad574f41b61d9f4457e0106b41b8 100644 (file)
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -413,46 +413,78 @@ u32 *get_periph_source_reg(enum periph_id periph_id)
        return &clkrst->crc_clk_src[internal_id];
 }
 
-/**
- * Given a peripheral ID and the required source clock, this returns which
- * value should be programmed into the source mux for that peripheral.
- *
- * There is special code here to handle the one source type with 5 sources.
- *
- * @param periph_id    peripheral to start
- * @param source       PLL id of required parent clock
- * @param mux_bits     Set to number of bits in mux register: 2 or 4
- * @param divider_bits Set to number of divider bits (8 or 16)
- * @return mux value (0-4, or -1 if not found)
- */
-int get_periph_clock_source(enum periph_id periph_id,
-               enum clock_id parent, int *mux_bits, int *divider_bits)
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+                         int *divider_bits, int *type)
 {
-       enum clock_type_id type;
        enum periphc_internal_id internal_id;
-       int mux;
 
-       assert(clock_periph_id_isvalid(periph_id));
+       if (!clock_periph_id_isvalid(periph_id))
+               return -1;
 
        internal_id = periph_id_to_internal_id[periph_id];
-       assert(periphc_internal_id_isvalid(internal_id));
+       if (!periphc_internal_id_isvalid(internal_id))
+               return -1;
 
-       type = clock_periph_type[internal_id];
-       assert(clock_type_id_isvalid(type));
+       *type = clock_periph_type[internal_id];
+       if (!clock_type_id_isvalid(*type))
+               return -1;
 
        /*
         * Special cases here for the clock with a 4-bit source mux and I2C
         * with its 16-bit divisor
         */
-       if (type == CLOCK_TYPE_PCXTS)
+       if (*type == CLOCK_TYPE_PCXTS)
                *mux_bits = MASK_BITS_31_28;
        else
                *mux_bits = MASK_BITS_31_30;
-       if (type == CLOCK_TYPE_PCMT16)
+       if (*type == CLOCK_TYPE_PCMT16)
                *divider_bits = 16;
        else
                *divider_bits = 8;
 
+       return 0;
+}
+
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
+{
+       enum periphc_internal_id internal_id;
+       int type;
+
+       if (!clock_periph_id_isvalid(periph_id))
+               return CLOCK_ID_NONE;
+
+       internal_id = periph_id_to_internal_id[periph_id];
+       if (!periphc_internal_id_isvalid(internal_id))
+               return CLOCK_ID_NONE;
+
+       type = clock_periph_type[internal_id];
+       if (!clock_type_id_isvalid(type))
+               return CLOCK_ID_NONE;
+
+       return clock_source[type][source];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id    peripheral to start
+ * @param source       PLL id of required parent clock
+ * @param mux_bits     Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+               enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+       enum clock_type_id type;
+       int mux, err;
+
+       err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
+       assert(!err);
+
        for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
                if (clock_source[type][mux] == parent)
                        return mux;
@@ -717,3 +749,24 @@ int tegra_plle_enable(void)
 
        return 0;
 }
+
+struct periph_clk_init periph_clk_init_table[] = {
+       { PERIPH_ID_SPI1, CLOCK_ID_PERIPH },
+       { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
+       { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
+       { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
+       { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
+       { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
+       { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
+       { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
+       { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
+       { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
+       { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
+       { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
+       { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+       { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
+       { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
+       { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
+       { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
+       { -1, },
+};