/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <libfdt.h>
+#include <linux/libfdt.h>
#include <linux/kernel.h>
#include "init.h"
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
-static const struct uniphier_board_data ph1_sld3_data = {
- .dram_ch0_base = 0x80000000,
- .dram_ch0_size = 0x20000000,
- .dram_ch0_width = 32,
- .dram_ch1_base = 0xc0000000,
- .dram_ch1_size = 0x20000000,
- .dram_ch1_width = 16,
- .dram_ch2_base = 0xc0000000,
- .dram_ch2_size = 0x10000000,
- .dram_ch2_width = 16,
- .dram_freq = 1600,
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+static const struct uniphier_board_data uniphier_ld4_data = {
+ .dram_freq = 1600,
+ .dram_ch[0] = {
+ .size = 0x10000000,
+ .width = 16,
+ },
+ .dram_ch[1] = {
+ .size = 0x10000000,
+ .width = 16,
+ },
+ .flags = UNIPHIER_BD_DDR3PLUS,
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
-static const struct uniphier_board_data ph1_ld4_data = {
- .dram_ch0_base = 0x80000000,
- .dram_ch0_size = 0x10000000,
- .dram_ch0_width = 16,
- .dram_ch1_base = 0x90000000,
- .dram_ch1_size = 0x10000000,
- .dram_ch1_width = 16,
- .dram_freq = 1600,
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+/* 1GB RAM board */
+static const struct uniphier_board_data uniphier_pro4_data = {
+ .dram_freq = 1600,
+ .dram_ch[0] = {
+ .size = 0x20000000,
+ .width = 32,
+ },
+ .dram_ch[1] = {
+ .size = 0x20000000,
+ .width = 32,
+ },
};
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
-static const struct uniphier_board_data ph1_pro4_data = {
- .dram_ch0_base = 0x80000000,
- .dram_ch0_size = 0x20000000,
- .dram_ch0_width = 32,
- .dram_ch1_base = 0xa0000000,
- .dram_ch1_size = 0x20000000,
- .dram_ch1_width = 32,
- .dram_freq = 1600,
+/* 2GB RAM board */
+static const struct uniphier_board_data uniphier_pro4_2g_data = {
+ .dram_freq = 1600,
+ .dram_ch[0] = {
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .dram_ch[1] = {
+ .size = 0x40000000,
+ .width = 32,
+ },
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
-static const struct uniphier_board_data ph1_sld8_data = {
- .dram_ch0_base = 0x80000000,
- .dram_ch0_size = 0x10000000,
- .dram_ch0_width = 16,
- .dram_ch1_base = 0x90000000,
- .dram_ch1_size = 0x10000000,
- .dram_ch1_width = 16,
- .dram_freq = 1333,
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+static const struct uniphier_board_data uniphier_sld8_data = {
+ .dram_freq = 1333,
+ .dram_ch[0] = {
+ .size = 0x10000000,
+ .width = 16,
+ },
+ .dram_ch[1] = {
+ .size = 0x10000000,
+ .width = 16,
+ },
+ .flags = UNIPHIER_BD_DDR3PLUS,
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
-static const struct uniphier_board_data ph1_pro5_data = {
- .dram_ch0_base = 0x80000000,
- .dram_ch0_size = 0x20000000,
- .dram_ch0_width = 32,
- .dram_ch1_base = 0xa0000000,
- .dram_ch1_size = 0x20000000,
- .dram_ch1_width = 32,
- .dram_freq = 1866,
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+static const struct uniphier_board_data uniphier_pro5_data = {
+ .dram_freq = 1866,
+ .dram_ch[0] = {
+ .size = 0x20000000,
+ .width = 32,
+ },
+ .dram_ch[1] = {
+ .size = 0x20000000,
+ .width = 32,
+ },
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
-static const struct uniphier_board_data proxstream2_data = {
- .dram_ch0_base = 0x80000000,
- .dram_ch0_size = 0x40000000,
- .dram_ch0_width = 32,
- .dram_ch1_base = 0xc0000000,
- .dram_ch1_size = 0x20000000,
- .dram_ch1_width = 32,
- .dram_ch2_base = 0xe0000000,
- .dram_ch2_size = 0x20000000,
- .dram_ch2_width = 16,
- .dram_freq = 2133,
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+static const struct uniphier_board_data uniphier_pxs2_data = {
+ .dram_freq = 2133,
+ .dram_ch[0] = {
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .dram_ch[1] = {
+ .size = 0x20000000,
+ .width = 32,
+ },
+ .dram_ch[2] = {
+ .size = 0x20000000,
+ .width = 16,
+ },
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
-static const struct uniphier_board_data ph1_ld6b_data = {
- .dram_ch0_base = 0x80000000,
- .dram_ch0_size = 0x40000000,
- .dram_ch0_width = 32,
- .dram_ch1_base = 0xc0000000,
- .dram_ch1_size = 0x20000000,
- .dram_ch1_width = 32,
- .dram_ch2_base = 0xe0000000,
- .dram_ch2_size = 0x20000000,
- .dram_ch2_width = 16,
- .dram_freq = 1866,
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+static const struct uniphier_board_data uniphier_ld6b_data = {
+ .dram_freq = 1866,
+ .dram_ch[0] = {
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .dram_ch[1] = {
+ .size = 0x20000000,
+ .width = 32,
+ },
+ .dram_ch[2] = {
+ .size = 0x20000000,
+ .width = 16,
+ },
};
#endif
};
static const struct uniphier_board_id uniphier_boards[] = {
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- { "socionext,ph1-sld3", &ph1_sld3_data, },
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
- { "socionext,ph1-ld4", &ph1_ld4_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+ { "socionext,uniphier-ld4", &uniphier_ld4_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
- { "socionext,ph1-pro4", &ph1_pro4_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+ { "socionext,uniphier-pro4-ace", &uniphier_pro4_2g_data, },
+ { "socionext,uniphier-pro4-sanji", &uniphier_pro4_2g_data, },
+ { "socionext,uniphier-pro4", &uniphier_pro4_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- { "socionext,ph1-sld8", &ph1_sld8_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ { "socionext,uniphier-sld8", &uniphier_sld8_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- { "socionext,ph1-pro5", &ph1_pro5_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ { "socionext,uniphier-pro5", &uniphier_pro5_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
- { "socionext,proxstream2", &proxstream2_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+ { "socionext,uniphier-pxs2", &uniphier_pxs2_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- { "socionext,ph1-ld6b", &ph1_ld6b_data, },
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ { "socionext,uniphier-ld6b", &uniphier_ld6b_data, },
#endif
};
projects / u-boot / blobdiff