ARM: uniphier: fix DSPLL init code for LD20 SoC

[u-boot] / arch / arm / mach-uniphier / clk / clk-ld11.c

diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
index b1e82a150a49ddc3b617eb9c40e40ddb05550198..0266e7e66b79d849d29d1fdca11d59a004795e3f 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-ld11.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -13,6 +13,8 @@
 #include "../sc64-regs.h"
 #include "../sg-regs.h"
 
+#define SDCTRL_EMMC_HW_RESET   0x59810280
+
 void uniphier_ld11_clk_init(void)
 {
        /* if booted from a device other than USB, without stand-by MPU */
@@ -28,13 +30,25 @@ void uniphier_ld11_clk_init(void)
                writel(7, SG_ETPHYCNT);
        }
 
-#ifdef CONFIG_USB_EHCI
+       /* TODO: use "mmc-pwrseq-emmc" */
+       writel(1, SDCTRL_EMMC_HW_RESET);
+
+#ifdef CONFIG_USB_EHCI_HCD
        {
                /* FIXME: the current clk driver can not handle parents */
                u32 tmp;
+               int ch;
+
                tmp = readl(SC_CLKCTRL4);
                tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
                writel(tmp, SC_CLKCTRL4);
+
+               for (ch = 0; ch < 3; ch++) {
+                       void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL;
+
+                       writel(0x82280600, phyctrl + 8 * ch);
+                       writel(0x00000106, phyctrl + 8 * ch + 4);
+               }
        }
 #endif
 }