ARM: uniphier: add PXs3 SoC support

[u-boot] / arch / arm / mach-uniphier / clk / dpll-ld20.c

diff --git a/arch/arm/mach-uniphier/clk/dpll-ld20.c b/arch/arm/mach-uniphier/clk/dpll-ld20.c
index 113231307a4945776f82c4fca8c41ffa69096932..86e99c4d1f0e75086705d0d9897d8bcb2a216727 100644 (file)
--- a/arch/arm/mach-uniphier/clk/dpll-ld20.c
+++ b/arch/arm/mach-uniphier/clk/dpll-ld20.c
@@ -11,12 +11,9 @@
 
 int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
 {
-       unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
-       unsigned int dram_freq = bd->dram_freq;
-
-       uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2);
-       uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2);
-       uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2);
+       uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+       uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+       uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
 
        return 0;
 }