Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh

[u-boot] / arch / arm / mach-uniphier / clk / pll-ld11.c

diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index 7746deb72d1d1067ac1ca28d0313d2473e54ec34..1a7ec295252408a9aca747334c49fdb9af7e83ad 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -4,13 +4,24 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#include <common.h>
+#include <linux/delay.h>
 #include <linux/io.h>
 
 #include "../init.h"
 #include "../sc64-regs.h"
 #include "pll.h"
 
+/* PLL type: SSC */
+#define SC_CPLLCTRL    (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
+#define SC_SPLLCTRL    (SC_BASE_ADDR | 0x1410) /* misc */
+#define SC_MPLLCTRL    (SC_BASE_ADDR | 0x1430) /* DSP */
+#define SC_VSPLLCTRL   (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
+#define SC_DPLLCTRL    (SC_BASE_ADDR | 0x1460) /* DDR memory */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
 void uniphier_ld11_pll_init(void)
 {
        uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2);     /* 2000MHz -> 1960MHz */
@@ -18,6 +29,8 @@ void uniphier_ld11_pll_init(void)
        uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2);     /* 1500MHz -> 1600MHz */
        uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
 
+       uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5);
+
        mdelay(1);
 
        uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);