/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/processor.h>
#include "../init.h"
-#include "ddrphy-regs.h"
+#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
int ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
writel(0x00000101, dc_base + UMC_DIOCTLA);
- ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
+ ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
if (ret)
return ret;
return umc_dramcont_init(dc_base, ca_base, freq, size, ddr3plus);
}
-int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
+int uniphier_sld8_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *umc_base = (void __iomem *)0x5b800000;
void __iomem *ca_base = umc_base + 0x00001000;
for (ch = 0; ch < DRAM_CH_NR; ch++) {
ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
bd->dram_ch[ch].size,
- bd->dram_ddr3plus, ch);
+ !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;