ARM: UniPhier: fix typos in comments

[u-boot] / arch / arm / mach-uniphier / lowlevel_init.S

diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index 3a3ada8fce72976594abe484dc271e93382c0635..4a23ea4d560d2d965017835d9eb91cb1bb3a66f5 100644 (file)
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -25,8 +25,8 @@ ENTRY(lowlevel_init)
         * First we need to turn on MMU and Dcache again to get back
         * data access to L2.
         */
-       mrc     p15, 0, r0, c1, c0, 0           @ SCTLR (System Contrl Register)
-       orr     r0, r0, #(CR_C | CR_M)          @ enable MMU and Dcache
+       mrc     p15, 0, r0, c1, c0, 0   @ SCTLR (System Control Register)
+       orr     r0, r0, #(CR_C | CR_M)  @ enable MMU and Dcache
        mcr     p15, 0, r0, c1, c0, 0
 
 #ifdef CONFIG_DEBUG_LL
@@ -41,7 +41,7 @@ ENTRY(lowlevel_init)
        ldr     r3, =init_page_table    @ page table must be 16KB aligned
 
        /* Disable MMU and Dcache before switching Page Table */
-       mrc     p15, 0, r0, c1, c0, 0   @ SCTLR (System Contrl Register)
+       mrc     p15, 0, r0, c1, c0, 0   @ SCTLR (System Control Register)
        bic     r0, r0, #(CR_C | CR_M)  @ disable MMU and Dcache
        mcr     p15, 0, r0, c1, c0, 0
 
@@ -55,7 +55,7 @@ ENTRY(lowlevel_init)
         * bit[7]  EXCL (Exclusive cache bit)
         * bit[6]  SMP
         * bit[3]  Write full line of zeros mode
-        * bit[2]  L1 Prefetch enable
+        * bit[2]  L1 prefetch enable
         * bit[1]  L2 prefetch enable
         * bit[0]  FW (Cache and TLB maintenance broadcast)
         */
@@ -81,7 +81,7 @@ primary_cpu:
        ldr     r0, =_start             @ entry for the secondary CPU
        str     r0, [r1]
        ldr     r0, [r1]                @ make sure str is complete before sev
-       sev                             @ kick the sedoncary CPU
+       sev                             @ kick the secondary CPU
        mrc     p15, 4, r1, c15, c0, 0  @ Configuration Base Address Register
        bfc     r1, #0, #13             @ clear bit 12-0
        mov     r0, #-1
@@ -118,7 +118,7 @@ ENTRY(enable_mmu)
         * TLBs was already invalidated in "../start.S"
         * So, we don't need to invalidate it here.
         */
-       mrc     p15, 0, r0, c1, c0, 0   @ SCTLR (System Contrl Register)
+       mrc     p15, 0, r0, c1, c0, 0   @ SCTLR (System Control Register)
        orr     r0, r0, #(CR_C | CR_M)  @ MMU and Dcache enable
        mcr     p15, 0, r0, c1, c0, 0
 
@@ -155,7 +155,7 @@ ENTRY(setup_init_ram)
        ldr     r1, = SSCOPPQSEF
        ldr     r0, [r1]
        cmp     r0, #0                  @ check if the command is successfully set
-       bne     0b                      @ try again if an error occurres
+       bne     0b                      @ try again if an error occurs
 
        ldr     r1, = SSCOLPQS
 1: