Merge branch 'master' of git://git.denx.de/u-boot-uniphier

[u-boot] / arch / arm / mach-uniphier / ph1-ld4 / sbc_init.c

diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
index 374a8c06800bc5632b940b9324961d02c7f37138..00f84614f68174d6285fc8cd1082dccd075d2e88 100644 (file)
--- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
+++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
@@ -19,32 +19,32 @@ void sbc_init(void)
        tmp &= 0xfffffcff;
        writel(tmp, PC0CTRL);
 
-       /* XECS1: sub/boot memory (boot swap = off/on) */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-       /* XECS0: boot/sub memory (boot swap = off/on) */
-       writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-       writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-       writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-       writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-
-       /* XECS3: peripherals */
-       writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
-       writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
-       writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
-       writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
-       /* base address regsiters */
-       writel(0x0000bc01, SBBASE0);
-       writel(0x0400bc01, SBBASE1);
-       writel(0x0800bf01, SBBASE3);
-
-       /* enable access to sub memory when boot swap is on */
-       if (boot_is_swapped())
-               sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-
-       sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
+       /*
+        * Only CS1 is connected to support card.
+        * BKSZ[1:0] should be set to "01".
+        */
+       writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+       writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+       writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+       writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+       if (boot_is_swapped()) {
+               /*
+                * Boot Swap On: boot from external NOR/SRAM
+                * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
+                *
+                * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
+                * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
+                */
+               writel(0x0000bc01, SBBASE0);
+       } else {
+               /*
+                * Boot Swap Off: boot from mask ROM
+                * 0x00000000-0x01ffffff: mask ROM
+                * 0x02000000-0x03efffff: memory bank (31MB)
+                * 0x03f00000-0x03ffffff: peripherals (1MB)
+                */
+               writel(0x0000be01, SBBASE0); /* dummy */
+               writel(0x0200be01, SBBASE1);
+       }
 }